Lines Matching defs:Worklist
5156 SetVectorType Worklist;
5157 Worklist.insert(&TopInst);
5159 while (!Worklist.empty()) {
5160 MachineInstr &Inst = *Worklist.pop_back_val();
5173 splitScalar64BitAddSub(Worklist, Inst, MDT);
5179 if (moveScalarAddSub(Worklist, Inst, MDT))
5185 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT);
5190 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32, MDT);
5195 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32, MDT);
5200 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NAND_B32, MDT);
5205 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NOR_B32, MDT);
5211 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XNOR_B32, MDT);
5213 splitScalar64BitXnor(Worklist, Inst, MDT);
5218 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ANDN2_B32, MDT);
5223 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ORN2_B32, MDT);
5228 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
5233 splitScalar64BitBCNT(Worklist, Inst);
5238 splitScalar64BitBFE(Worklist, Inst);
5280 lowerScalarAbs(Worklist, Inst);
5306 movePackToVALU(Worklist, MRI, Inst);
5311 lowerScalarXnor(Worklist, Inst);
5316 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_AND_B32);
5321 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_OR_B32);
5326 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_AND_B32);
5331 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);
5366 addUsersToMoveToVALUWorklist(DestReg, MRI, Worklist);
5394 Worklist);
5401 lowerSelect(Worklist, Inst, MDT);
5425 addSCCDefUsersToVALUWorklist(Op, Inst, Worklist);
5482 addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
5504 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
5509 bool SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
5537 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5544 void SIInstrInfo::lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
5613 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5616 void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,
5640 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5643 void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
5664 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5697 Worklist.insert(Not);
5702 Worklist.insert(Xor);
5704 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5708 void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,
5730 Worklist.insert(&Op);
5731 Worklist.insert(&Not);
5734 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5737 void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,
5759 Worklist.insert(&Not);
5760 Worklist.insert(&Op);
5763 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5767 SetVectorType &Worklist, MachineInstr &Inst,
5810 Worklist.insert(&LoHalf);
5811 Worklist.insert(&HiHalf);
5817 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5820 void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,
5889 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5892 void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,
5949 Worklist.insert(&LoHalf);
5950 Worklist.insert(&HiHalf);
5953 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5956 void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,
5995 Worklist.insert(&Xor);
5999 SetVectorType &Worklist, MachineInstr &Inst) const {
6032 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6035 void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,
6074 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6093 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6099 SetVectorType &Worklist) const {
6121 Worklist.insert(&UseMI);
6132 void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,
6191 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
6196 SetVectorType &Worklist) const {
6218 Worklist.insert(&User);
6221 // No need to add to Worklist.
6237 Worklist.insert(&MI);