Lines Matching defs:SRsrc
4685 Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4697 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
4708 Rsrc.setReg(SRsrc);
4713 .addReg(SRsrc, 0, AMDGPU::sub0_sub1)
4716 .addReg(SRsrc, 0, AMDGPU::sub2_sub3)
4989 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
4990 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4991 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
4992 SRsrc->setReg(SGPR);
5021 // a zero-value SRsrc.