Lines Matching defs:Rsrc
4654 // unique value of \p Rsrc across all lanes. In the best case we execute 1
4659 const DebugLoc &DL, MachineOperand &Rsrc) {
4674 Register VRsrc = Rsrc.getReg();
4675 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
4687 // Beginning of the loop, read the next Rsrc variant.
4707 // Update Rsrc operand to use the SGPR Rsrc.
4708 Rsrc.setReg(SRsrc);
4709 Rsrc.setIsKill(true);
4711 // Identify all lanes with identical Rsrc operands in their VGPRs.
4738 // Build a waterfall loop around \p MI, replacing the VGPR \p Rsrc register
4741 MachineOperand &Rsrc, MachineDominatorTree *MDT) {
4801 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);
4808 // Extract pointer from Rsrc and return a zero-value Rsrc replacement.
4810 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
4817 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass,
5008 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
5010 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
5017 // Legalize a VGPR Rsrc.
5020 // the base pointer from the VGPR Rsrc, adding it to the VAddr, then using
5045 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
5071 Rsrc->setReg(NewSRsrc);
5080 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
5147 // This is another variant; legalize Rsrc with waterfall loop from VGPRs
5149 loadSRsrcFromVGPR(*this, MI, *Rsrc, MDT);