Lines Matching defs:LoopBB
4658 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
4672 MachineBasicBlock::iterator I = LoopBB.begin();
4688 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
4690 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
4692 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
4694 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
4697 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
4712 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
4715 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
4718 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndCond)
4725 BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec)
4729 I = LoopBB.end();
4732 BuildMI(LoopBB, I, DL, TII.get(XorTermOpc), Exec)
4735 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
4768 MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock();
4773 MF.insert(MBBI, LoopBB);
4776 LoopBB->addSuccessor(LoopBB);
4777 LoopBB->addSuccessor(RemainderBB);
4779 // Move MI to the LoopBB, and the remainder of the block to RemainderBB.
4783 LoopBB->splice(LoopBB->begin(), &MBB, J);
4785 MBB.addSuccessor(LoopBB);
4787 // Update dominators. We know that MBB immediately dominates LoopBB, that
4788 // LoopBB immediately dominates RemainderBB, and that RemainderBB immediately
4792 MDT->addNewBlock(LoopBB, &MBB);
4793 MDT->addNewBlock(RemainderBB, LoopBB);
4801 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);