Lines Matching defs:DL
463 const DataLayout &DL = MF.getFunction().getParent()->getDataLayout();
464 Base1 = GetUnderlyingObject(Base1, DL);
465 Base2 = GetUnderlyingObject(Base2, DL);
524 const DebugLoc &DL, MCRegister DestReg,
528 DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(), Msg, DL, DS_Error);
532 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
538 const DebugLoc &DL, MCRegister DestReg,
554 BuildMI(MBB, MI, DL, get(AMDGPU::BUNDLE));
567 BuildMI(MBB, MI, DL, get(Opc), DestReg)
575 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
583 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
588 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
597 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
601 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
608 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B64), DestReg)
616 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
621 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
630 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
634 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
648 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
685 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
716 copyPhysReg(MBB, MI, DL, Tmp, SrcReg, KillSrc);
717 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
722 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
748 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
752 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), NewDestReg)
759 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
763 copyPhysReg(MBB, MI, DL, NewDestReg, NewSrcReg, KillSrc);
769 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc,
773 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), NewDestReg)
778 auto MIB = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_sdwa), NewDestReg)
806 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
827 copyPhysReg(MBB, MI, DL, RI.getSubReg(DestReg, SubIdx),
832 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
865 const DebugLoc &DL, unsigned DestReg,
873 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
881 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
887 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
892 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
913 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
926 const DebugLoc &DL, Register DstReg,
940 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
942 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
953 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
957 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
967 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
971 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
983 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
985 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
997 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
999 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1010 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1013 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1017 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1028 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1031 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
1035 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1054 const DebugLoc &DL,
1058 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
1067 const DebugLoc &DL,
1071 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1242 const DebugLoc &DL = MBB.findDebugLoc(MI);
1268 BuildMI(MBB, MI, DL, OpDesc)
1286 auto MIB = BuildMI(MBB, MI, DL, get(Opcode));
1375 const DebugLoc &DL = MBB.findDebugLoc(MI);
1401 BuildMI(MBB, MI, DL, OpDesc, DestReg)
1411 auto MIB = BuildMI(MBB, MI, DL, get(Opcode), DestReg);
1431 const DebugLoc &DL = MBB.findDebugLoc(MI);
1439 const DebugLoc &DL = Insert->getDebugLoc();
1465 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
1468 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
1473 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
1477 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
1481 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
1486 getAddNoCarry(Entry, Insert, DL, TIDReg)
1492 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
1497 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
1503 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
1512 getAddNoCarry(MBB, MI, DL, TmpReg)
1523 DebugLoc DL = MBB.findDebugLoc(MI);
1531 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
1570 DebugLoc DL = MBB.findDebugLoc(MI);
1625 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1628 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1633 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1636 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1650 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1652 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1654 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1662 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1664 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1668 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1712 BuildMI(MBB, MI, DL, OpDesc)
1734 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
1738 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1742 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1774 DebugLoc DL = MBB.findDebugLoc(MI);
1783 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
1817 BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
1981 const DebugLoc &DL,
2000 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
2004 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
2008 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
2014 BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
2018 BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
2025 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2261 const DebugLoc &DL,
2264 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2272 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
2286 BuildMI(&MBB, DL, get(Opcode))
2301 BuildMI(&MBB, DL, get(Opcode))
2303 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2371 MachineBasicBlock::iterator I, const DebugLoc &DL,
2387 Select = BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B32), DstReg)
2392 Select = BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e32), DstReg)
2403 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
2445 MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
2459 BuildMI(MBB, I, DL, get(SelOp), DstElt)
2464 BuildMI(MBB, I, DL, get(SelOp), DstElt)
4185 DebugLoc DL = MBB->findDebugLoc(I);
4186 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
4198 DebugLoc DL = MI->getDebugLoc();
4202 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4213 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
4216 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4373 const DebugLoc &DL = MI.getDebugLoc();
4376 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4382 const DebugLoc &DL = MI.getDebugLoc();
4383 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4408 const DebugLoc &DL = MI.getDebugLoc();
4409 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4477 const DebugLoc &DL = MI.getDebugLoc();
4480 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4486 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4615 const DebugLoc &DL) const {
4628 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
4659 const DebugLoc &DL, MachineOperand &Rsrc) {
4688 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
4690 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
4692 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
4694 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
4697 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
4712 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
4715 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
4718 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndCond)
4725 BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec)
4732 BuildMI(LoopBB, I, DL, TII.get(XorTermOpc), Exec)
4735 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
4748 const DebugLoc &DL = MI.getDebugLoc();
4756 BuildMI(MBB, I, DL, TII.get(MovExecOpc), SaveExec).addReg(Exec);
4801 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);
4805 BuildMI(*RemainderBB, First, DL, TII.get(MovExecOpc), Exec).addReg(SaveExec);
5048 const DebugLoc &DL = MI.getDebugLoc();
5049 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e64), NewVAddrLo)
5056 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e64), NewVAddrHi)
5372 const DebugLoc &DL = Inst.getDebugLoc();
5384 MachineInstr *NewInstr = BuildMI(*MBB, &Inst, DL, get(Opc), DestReg)
5550 DebugLoc DL = Inst.getDebugLoc();
5595 BuildMI(MBB, MII, DL, get(Opcode), CopySCC).addImm(-1).addImm(0);
5598 BuildMI(MBB, MII, DL, get(AMDGPU::COPY), CopySCC).addReg(SCCSource);
5604 BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg)
5621 DebugLoc DL = Inst.getDebugLoc();
5631 BuildMI(MBB, MII, DL, get(SubOp), TmpReg)
5635 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5648 const DebugLoc &DL = Inst.getDebugLoc();
5656 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
5657 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src1, MRI, DL);
5659 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest)
5682 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
5683 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5687 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src1);
5688 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5692 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
5696 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp);
5714 const DebugLoc &DL = Inst.getDebugLoc();
5723 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
5727 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
5743 const DebugLoc &DL = Inst.getDebugLoc();
5752 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm)
5755 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest)
5774 DebugLoc DL = Inst.getDebugLoc();
5793 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
5799 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
5802 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5839 const DebugLoc &DL = Inst.getDebugLoc();
5860 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
5868 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
5875 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5901 DebugLoc DL = Inst.getDebugLoc();
5931 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
5936 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
5941 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5965 const DebugLoc &DL = Inst.getDebugLoc();
5984 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm)
5989 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
6004 const DebugLoc &DL = Inst.getDebugLoc();
6024 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
6026 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
6040 const DebugLoc &DL = Inst.getDebugLoc();
6058 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
6063 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
6067 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
6082 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
6086 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
6139 const DebugLoc &DL = Inst.getDebugLoc();
6148 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6151 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg)
6155 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
6163 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6165 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
6174 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
6177 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
6179 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
6710 const DebugLoc &DL,
6713 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg);
6719 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
6725 const DebugLoc &DL,
6729 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e32), DestReg);
6740 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
7073 const DebugLoc &DL, Register Src, Register Dst) const {
7078 return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
7082 return TargetInstrInfo::createPHIDestinationCopy(MBB, LastPHIIt, DL, Src,
7088 const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const {
7095 return BuildMI(MBB, InsPt, DL,
7102 return TargetInstrInfo::createPHISourceCopy(MBB, InsPt, DL, Src, SrcSubReg,