Lines Matching refs:ScratchRsrcReg
136 Register ScratchRsrcReg, Register SPReg, int FI) {
149 .addReg(ScratchRsrcReg)
170 .addReg(ScratchRsrcReg)
184 Register ScratchRsrcReg, Register SPReg, int FI) {
196 .addReg(ScratchRsrcReg)
217 .addReg(ScratchRsrcReg)
317 Register ScratchRsrcReg = MFI->getScratchRSrcReg();
319 if (!ScratchRsrcReg || !MRI.isPhysRegUsed(ScratchRsrcReg))
323 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))
324 return ScratchRsrcReg;
348 MRI.replaceRegWith(ScratchRsrcReg, Reg);
354 return ScratchRsrcReg;
393 Register ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);
396 if (ScratchRsrcReg) {
399 OtherBB.addLiveIn(ScratchRsrcReg);
410 if (ScratchRsrcReg && PreloadedScratchRsrcReg) {
429 if (TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {
437 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {
462 if (MFI->hasFlatScratchInit() || ScratchRsrcReg) {
471 if (ScratchRsrcReg) {
474 ScratchRsrcReg, ScratchWaveOffsetReg);
478 // Emit scratch RSRC setup code, assuming `ScratchRsrcReg != AMDGPU::NoReg`
482 Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const {
493 Register RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
494 Register RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
495 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
502 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
512 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
526 BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
531 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
537 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
538 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
544 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
551 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
567 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
573 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
574 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
578 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
582 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
588 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
592 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
596 if (ScratchRsrcReg != PreloadedScratchRsrcReg) {
597 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
611 Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
612 Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
619 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
623 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);