Lines Matching defs:DL
231 const DebugLoc &DL, Register ScratchWaveOffsetReg) const {
260 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
263 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), FlatScrInitHi)
266 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
270 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
277 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
280 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
290 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
295 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
300 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
420 DebugLoc DL;
439 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)
452 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), SPReg)
459 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), FPReg).addImm(0);
468 emitEntryFunctionFlatScratchInit(MF, MBB, I, DL, ScratchWaveOffsetReg);
472 emitEntryFunctionScratchRsrcRegSetup(MF, MBB, I, DL,
481 const DebugLoc &DL, Register PreloadedScratchRsrcReg,
500 BuildMI(MBB, I, DL, SMovB32, RsrcHi)
505 BuildMI(MBB, I, DL, GetPC64, Rsrc01);
510 BuildMI(MBB, I, DL, SMovB32, RsrcLo)
526 BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
549 BuildMI(MBB, I, DL, Mov64, Rsrc01)
561 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
576 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
580 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
586 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
590 BuildMI(MBB, I, DL, SMovB32, Rsrc3)
597 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
616 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), ScratchRsrcSub0)
620 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), ScratchRsrcSub1)
650 DebugLoc DL;
677 BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), ScratchExecCopy).addImm(-1);
703 DebugLoc DL;
733 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->SGPRForFPSaveRestoreCopy)
740 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY),
787 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
804 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
816 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
833 BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
852 BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
878 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg)
882 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
888 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
898 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), BasePtrReg)
904 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg)
939 DebugLoc DL;
966 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)
973 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
979 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), BasePtrReg)
996 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), FramePtrReg)
1004 BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
1022 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), BasePtrReg)
1030 BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
1054 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
1242 const DebugLoc &DL = I->getDebugLoc();
1254 BuildMI(MBB, I, DL, TII->get(Op), SPReg)