Lines Matching refs:TII
65 const SIInstrInfo *TII = ST.getInstrInfo();
78 if (TII->isMIMG(Opcode) && !MI.mayStore()) {
79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe);
80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe);
81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16);
103 TII->getNamedOperand(MI, AMDGPU::OpName::dmask);
112 TII->isGather4(Opcode) ? 4 : countPopulation(dmask);
123 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
129 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
140 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst)
144 BuildMI(MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), PrevDst);
147 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
151 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg)
154 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst)