Lines Matching refs:SDValue
35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
36 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
38 SmallVectorImpl<SDValue> &Results,
41 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
45 SmallVectorImpl<SDValue> &InVals) const override;
63 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
68 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
70 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
72 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
74 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
75 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
77 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
79 SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
80 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
82 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
84 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
93 SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
97 bool isZero(SDValue Op) const;
98 bool isHWTrueValue(SDValue Op) const;
99 bool isHWFalseValue(SDValue Op) const;
101 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
102 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
104 SDValue constBufferLoad(LoadSDNode *LoadNode, int Block,