Target/AMDGPU/R600ISelLowering.cpp

56 R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
292 R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
658 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
700 SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
715 SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
730 SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
747 SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
762 SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
796 SDValue R600TargetLowering::LowerSHLParts(SDValue Op, SelectionDAG &DAG) const {
832 SDValue R600TargetLowering::LowerSRXParts(SDValue Op, SelectionDAG &DAG) const {
870 SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
888 SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
898 SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
908 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
923 bool R600TargetLowering::isZero(SDValue Op) const {
933 bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
940 bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
947 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
1093 SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
1115 void R600TargetLowering::getStackAddress(unsigned StackWidth,
1144 SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
1234 SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1390 SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1446 SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1535 SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1544 SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1559 CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1584 SDValue R600TargetLowering::LowerFormalArguments(
1654 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1661 bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1670 bool R600TargetLowering::allowsMisalignedMemoryAccesses(
1774 SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
1798 SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block,
1848 SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
2075 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
2207 SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,