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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/

Lines Matching refs:TII

41   const R600InstrInfo *TII = nullptr;
75 int OpIdx = TII->getOperandIdx(*OldMI, Op);
78 TII->setImmOperand(*NewMI, Op, Val);
84 TII = ST.getInstrInfo();
86 const R600RegisterInfo &TRI = TII->getRegisterInfo();
97 if (TII->isLDSRetInstr(MI.getOpcode())) {
98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
101 MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
104 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
106 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
120 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
125 TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
127 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1);
129 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1);
136 const R600RegisterInfo &TRI = TII->getRegisterInfo();
146 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
151 TII->addFlag(*BMI, 0, MO_FLAG_MASK);
154 TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
159 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
162 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
175 bool IsReduction = TII->isReductionOp(MI.getOpcode());
176 bool IsVector = TII->isVector(MI);
177 bool IsCube = TII->isCubeOp(MI.getOpcode());
209 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
211 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
216 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1);
264 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
269 TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
272 TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);