Lines Matching refs:TII
45 TII(*ST.getInstrInfo()),
46 TRI(TII.getRegisterInfo()),
93 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII,
95 if (TII.isAlwaysGDS(MI.getOpcode()))
109 if (TII.isDS(MI.getOpcode())) {
125 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) {
126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,
177 (TII.isVINTRP(*MI) || isSMovRel(MI->getOpcode())) &&
181 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI) &&
200 static void insertNoopInBundle(MachineInstr *MI, const SIInstrInfo &TII) {
201 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP))
217 insertNoopInBundle(CurrCycleInstr, TII);
284 if (ST.hasReadM0MovRelInterpHazard() && (TII.isVINTRP(*MI) ||
288 if (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI))
322 unsigned NumWaitStates = TII.getNumWaitStates(*CurrCycleInstr);
498 bool IsSMRD = TII.isSMRD(*MEM);
552 auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };
553 auto IsBufferHazardDefFn = [this] (MachineInstr *MI) { return TII.isSALU(*MI); };
555 bool IsBufferSMRD = TII.isBufferSMRD(*SMRD);
593 auto IsHazardDefFn = [this] (MachineInstr *MI) { return TII.isVALU(*MI); };
608 const SIInstrInfo *TII = ST.getInstrInfo();
614 auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
635 const SIInstrInfo *TII = ST.getInstrInfo();
640 auto IsHazardDefFn = [TII] (MachineInstr *MI) { return TII->isVALU(*MI); };
648 const SIInstrInfo *TII = ST.getInstrInfo();
649 unsigned GetRegHWReg = getHWReg(TII, *GetRegInstr);
652 auto IsHazardFn = [TII, GetRegHWReg] (MachineInstr *MI) {
653 return GetRegHWReg == getHWReg(TII, *MI);
661 const SIInstrInfo *TII = ST.getInstrInfo();
662 unsigned HWReg = getHWReg(TII, *SetRegInstr);
665 auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
666 return HWReg == getHWReg(TII, *MI);
676 const SIInstrInfo *TII = ST.getInstrInfo();
685 if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
693 TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
705 if (TII->isMIMG(MI)) {
712 if (TII->isFLAT(MI)) {
788 const SIInstrInfo *TII = ST.getInstrInfo();
793 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);
799 auto IsHazardFn = [TII] (MachineInstr *MI) {
800 return TII->isVALU(*MI);
813 const SIInstrInfo *TII = ST.getInstrInfo();
817 auto IsHazardFn = [TII] (MachineInstr *MI) {
818 return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS;
853 const SIInstrInfo *TII = ST.getInstrInfo();
855 auto IsHazardFn = [TII] (MachineInstr *MI) {
856 return TII->isSALU(*MI);
874 const SIInstrInfo *TII = ST.getInstrInfo();
875 auto IsHazardFn = [TII] (MachineInstr *MI) {
876 return TII->isVOPC(*MI);
896 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
900 TII->get(AMDGPU::V_MOV_B32_e32))
943 const SIInstrInfo *TII = ST.getInstrInfo();
944 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_NOP_e32));
967 const SIInstrInfo *TII = ST.getInstrInfo();
970 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName);
988 auto IsExpiredFn = [TII, IV] (MachineInstr *MI, int) {
990 if (TII->isSALU(*MI)) {
1010 if (TII->isSOPP(*MI))
1031 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL)
1050 const SIInstrInfo *TII = ST.getInstrInfo();
1051 auto IsExpiredFn = [TII, TRI] (MachineInstr *MI, int) {
1055 if (TII->getNamedOperand(*MI, AMDGPU::OpName::sdst))
1072 TII->get(AMDGPU::S_WAITCNT_DEPCTR))
1130 const SIInstrInfo *TII = ST.getInstrInfo();
1132 TII->get(AMDGPU::S_WAITCNT_VSCNT))
1148 const SIInstrInfo *TII = ST.getInstrInfo();
1149 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
1153 auto IsHazardFn = [TII] (MachineInstr *I) {
1158 TII->getInstSizeInBytes(*I) >= 16;
1344 Register Reg = TII.getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg();