Lines Matching refs:AMDGPUDisassembler
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
19 #include "Disassembler/AMDGPUDisassembler.h"
59 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
65 // ToDo: AMDGPUDisassembler supports only VI ISA.
91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
105 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
117 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
126 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
172 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
196 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
197 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
204 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
205 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
213 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
220 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
228 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
229 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
252 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
279 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
443 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
463 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
484 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
614 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
620 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
630 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
635 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
645 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
684 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
688 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
692 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
696 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
700 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
704 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
713 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
717 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
721 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
725 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
729 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
733 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
737 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
741 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
745 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
749 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
753 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
757 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
761 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
768 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
774 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
780 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
787 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
791 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
795 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
799 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
803 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
807 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
822 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
907 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
928 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
943 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
962 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
979 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
996 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1007 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
1050 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1069 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1101 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1125 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1166 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1170 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1174 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1201 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1206 bool AMDGPUDisassembler::isVI() const {
1210 bool AMDGPUDisassembler::isGFX9() const {
1214 bool AMDGPUDisassembler::isGFX10() const {
1272 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());