Lines Matching defs:createRegOperand
453 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
630 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
635 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
641 return createRegOperand(RegCl.getRegister(Val));
681 return createRegOperand(SRegClassID, Val >> shift);
710 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
718 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
722 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
726 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
730 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
742 return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
746 return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
750 return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
754 return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
758 return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
1016 return createRegOperand(IsAGPR ? getAgprClassId(Width)
1073 case 102: return createRegOperand(FLAT_SCR_LO);
1074 case 103: return createRegOperand(FLAT_SCR_HI);
1075 case 104: return createRegOperand(XNACK_MASK_LO);
1076 case 105: return createRegOperand(XNACK_MASK_HI);
1077 case 106: return createRegOperand(VCC_LO);
1078 case 107: return createRegOperand(VCC_HI);
1079 case 108: return createRegOperand(TBA_LO);
1080 case 109: return createRegOperand(TBA_HI);
1081 case 110: return createRegOperand(TMA_LO);
1082 case 111: return createRegOperand(TMA_HI);
1083 case 124: return createRegOperand(M0);
1084 case 125: return createRegOperand(SGPR_NULL);
1085 case 126: return createRegOperand(EXEC_LO);
1086 case 127: return createRegOperand(EXEC_HI);
1087 case 235: return createRegOperand(SRC_SHARED_BASE);
1088 case 236: return createRegOperand(SRC_SHARED_LIMIT);
1089 case 237: return createRegOperand(SRC_PRIVATE_BASE);
1090 case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1091 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1092 case 251: return createRegOperand(SRC_VCCZ);
1093 case 252: return createRegOperand(SRC_EXECZ);
1094 case 253: return createRegOperand(SRC_SCC);
1095 case 254: return createRegOperand(LDS_DIRECT);
1105 case 102: return createRegOperand(FLAT_SCR);
1106 case 104: return createRegOperand(XNACK_MASK);
1107 case 106: return createRegOperand(VCC);
1108 case 108: return createRegOperand(TBA);
1109 case 110: return createRegOperand(TMA);
1110 case 125: return createRegOperand(SGPR_NULL);
1111 case 126: return createRegOperand(EXEC);
1112 case 235: return createRegOperand(SRC_SHARED_BASE);
1113 case 236: return createRegOperand(SRC_SHARED_LIMIT);
1114 case 237: return createRegOperand(SRC_PRIVATE_BASE);
1115 case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1116 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1117 case 251: return createRegOperand(SRC_VCCZ);
1118 case 252: return createRegOperand(SRC_EXECZ);
1119 case 253: return createRegOperand(SRC_SCC);
1136 return createRegOperand(getVgprClassId(Width),
1161 return createRegOperand(getVgprClassId(Width), Val);
1197 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);