Lines Matching defs:S32
130 const LLT S32 = LLT::scalar(32);
132 assert(MRI.getType(DstReg) == S32);
138 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1);
139 auto False = B.buildConstant(S32, 0);
889 LLT S32 = LLT::scalar(32);
916 Register CurrentLaneOpRegLo = MRI.createGenericVirtualRegister(S32);
917 Register CurrentLaneOpRegHi = MRI.createGenericVirtualRegister(S32);
950 CurrentLaneOpReg = MRI.createGenericVirtualRegister(S32);
1309 const LLT S32 = LLT::scalar(32);
1316 VOffsetReg = B.buildConstant(S32, 0).getReg(0);
1317 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1338 SOffsetReg = B.buildConstant(S32, SOffset).getReg(0);
1346 VOffsetReg = B.buildConstant(S32, 0).getReg(0);
1380 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0);
1384 SOffsetReg = B.buildConstant(S32, 0).getReg(0);
1394 const LLT S32 = LLT::scalar(32);
1446 Register VIndex = B.buildConstant(S32, 0).getReg(0);
1519 const LLT S32 = LLT::scalar(32);
1524 if (Ty == S32)
1543 auto OffsetMask = B.buildConstant(S32, maskTrailingOnes<unsigned>(6));
1544 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask);
1547 auto ShiftWidth = B.buildShl(S32, WidthReg, B.buildConstant(S32, 16));
1552 auto MergedInputs = B.buildOr(S32, ClampOffset, ShiftWidth);
1556 unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) :
1600 const LLT S32 = LLT::scalar(32);
1601 auto Bitcast = B.buildBitcast(S32, Src);
1604 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16);
1605 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16));
1609 auto ShiftHi = B.buildLShr(S32, Bitcast, B.buildConstant(S32, 16));
1611 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff));
1676 const LLT S32 = LLT::scalar(32);
1679 return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0);
1702 const LLT S32 = LLT::scalar(32);
1726 BaseReg = B.buildConstant(S32, Overflow).getReg(0);
1728 auto OverflowVal = B.buildConstant(S32, Overflow);
1729 BaseReg = B.buildAdd(S32, BaseReg, OverflowVal).getReg(0);
1735 BaseReg = B.buildConstant(S32, 0).getReg(0);
1875 const LLT S32 = LLT::scalar(32);
1879 auto MaterializedOffset = B.buildConstant(S32, ConstOffset);
1881 auto Add = B.buildAdd(S32, WaterfallIdx, MaterializedOffset);
1936 LLT S32 = LLT::scalar(32);
1948 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1);
1951 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
1969 auto IC = B.buildConstant(S32, I);
2018 LLT S32 = LLT::scalar(32);
2033 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1);
2036 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg();
2054 auto IC = B.buildConstant(S32, I);
2097 const LLT S32 = LLT::scalar(32);
2136 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2160 const LLT S32 = LLT::scalar(32);
2161 Register NewDstReg = MRI.createGenericVirtualRegister(S32);
2167 Register NewSrcReg = MRI.createGenericVirtualRegister(S32);
2198 const LLT S32 = LLT::scalar(32);
2199 Register NewCondReg = MRI.createGenericVirtualRegister(S32);
2250 const LLT S32 = LLT::scalar(32);
2251 Register NewCondReg = MRI.createGenericVirtualRegister(S32);
2355 const LLT S32 = LLT::scalar(32);
2372 auto Lo = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Lo, WideSrc1Lo});
2373 auto Hi = B.buildInstr(MI.getOpcode(), {S32}, {WideSrc0Hi, WideSrc1Hi});
2379 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2386 if (Helper.widenScalar(MI, 1, S32) != LegalizerHelper::Legalized)
2408 const LLT S32 = LLT::scalar(32);
2437 Register Lo = MRI.createGenericVirtualRegister(S32);
2438 Register Hi = MRI.createGenericVirtualRegister(S32);
2451 if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized)
2466 const LLT S32 = LLT::scalar(32);
2487 B.buildAShr(DstRegs[1], DstRegs[0], B.buildConstant(S32, 31));
2511 const LLT S32 = LLT::scalar(32);
2513 if (Ty == S32)
2520 if (Helper.narrowScalar(MI, 1, S32) != LegalizerHelper::Legalized)
2626 const LLT S32 = LLT::scalar(32);
2637 ZextLo = B.buildZExt(S32, Lo).getReg(0);
2640 Register ZextHi = B.buildZExt(S32, Hi).getReg(0);
2643 auto ShiftAmt = B.buildConstant(S32, 16);
2646 ShiftHi = B.buildShl(S32, ZextHi, ShiftAmt).getReg(0);
2649 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
2652 auto ShiftAmt = B.buildConstant(S32, 16);
2655 ShiftHi = B.buildShl(S32, Hi, ShiftAmt).getReg(0);
2658 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0);
2662 auto Or = B.buildOr(S32, ZextLo, ShiftHi);
2677 const LLT S32 = LLT::scalar(32);
2746 auto One = B.buildConstant(S32, 1);
2757 auto IdxLo = B.buildShl(S32, BaseIdxReg, One);
2758 auto IdxHi = B.buildAdd(S32, IdxLo, One);
2784 Register TmpReg0 = MRI.createGenericVirtualRegister(S32);
2785 Register TmpReg1 = MRI.createGenericVirtualRegister(S32);
2860 const LLT S32 = LLT::scalar(32);
2865 auto One = B.buildConstant(S32, 1);
2874 auto IdxLo = B.buildShl(S32, BaseIdxReg, One);
2875 auto IdxHi = B.buildAdd(S32, IdxLo, One);