Lines Matching defs:OpdMapper
1133 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
1141 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
1180 SmallVector<Register, 16> DefRegs(OpdMapper.getVRegs(0));
1181 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1));
1217 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
1266 MachineInstr &MI, const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
1275 applyDefaultMapping(OpdMapper);
1390 const OperandsMapper &OpdMapper) const {
1391 MachineInstr &MI = OpdMapper.getMI();
1392 MachineRegisterInfo &MRI = OpdMapper.getMRI();
1399 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
1401 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
1509 const OperandsMapper &OpdMapper, bool Signed) const {
1510 MachineInstr &MI = OpdMapper.getMI();
1511 MachineRegisterInfo &MRI = OpdMapper.getMRI();
1514 applyDefaultMapping(OpdMapper);
1522 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1646 const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, unsigned OpIdx) {
1647 SmallVector<unsigned, 1> SrcReg(OpdMapper.getVRegs(OpIdx));
1650 OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]);
1917 const OperandsMapper &OpdMapper) const {
1923 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
1939 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
1941 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
1956 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
1999 const OperandsMapper &OpdMapper) const {
2005 *OpdMapper.getInstrMapping().getOperandMapping(3).BreakDown[0].RegBank;
2021 *OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2023 *OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2025 *OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
2041 SmallVector<Register, 2> InsRegs(OpdMapper.getVRegs(2));
2086 const OperandsMapper &OpdMapper) const {
2087 MachineInstr &MI = OpdMapper.getMI();
2089 MachineRegisterInfo &MRI = OpdMapper.getMRI();
2099 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2101 applyDefaultMapping(OpdMapper);
2127 substituteSimpleCopyRegs(OpdMapper, 0);
2152 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2178 SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0));
2188 SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1));
2212 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2213 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2214 SmallVector<Register, 2> Src2Regs(OpdMapper.getVRegs(3));
2246 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2271 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2291 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2292 SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
2293 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
2351 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2399 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2462 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1));
2475 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
2506 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2531 assert(empty(OpdMapper.getVRegs(1)));
2535 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2546 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2571 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
2613 assert(MI.getNumOperands() == 3 && OpdMapper.getVRegs(0).empty());
2614 substituteSimpleCopyRegs(OpdMapper, 1);
2615 substituteSimpleCopyRegs(OpdMapper, 2);
2618 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2629 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2631 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
2670 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
2672 assert(OpdMapper.getVRegs(1).empty() && OpdMapper.getVRegs(2).empty());
2681 if (foldExtractEltToCmpSelect(MI, MRI, OpdMapper))
2687 = OpdMapper.getInstrMapping().getOperandMapping(0);
2690 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2692 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
2719 applyDefaultMapping(OpdMapper);
2804 SmallVector<Register, 2> InsRegs(OpdMapper.getVRegs(2));
2809 assert(OpdMapper.getVRegs(0).empty());
2810 assert(OpdMapper.getVRegs(3).empty());
2812 if (substituteSimpleCopyRegs(OpdMapper, 1))
2815 if (foldInsertEltToCmpSelect(MI, MRI, OpdMapper))
2819 OpdMapper.getInstrMapping().getOperandMapping(3).BreakDown[0].RegBank;
2881 OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
2883 OpdMapper.getInstrMapping().getOperandMapping(1).BreakDown[0].RegBank;
2885 OpdMapper.getInstrMapping().getOperandMapping(2).BreakDown[0].RegBank;
2940 applyDefaultMapping(OpdMapper);
2956 applyDefaultMapping(OpdMapper);
2961 applyDefaultMapping(OpdMapper);
2966 applyMappingSBufferLoad(OpdMapper);
2972 substituteSimpleCopyRegs(OpdMapper, 2);
2974 assert(OpdMapper.getVRegs(0).empty());
2975 assert(OpdMapper.getVRegs(3).empty());
2983 assert(OpdMapper.getVRegs(0).empty());
2984 assert(OpdMapper.getVRegs(2).empty());
2985 assert(OpdMapper.getVRegs(3).empty());
2987 substituteSimpleCopyRegs(OpdMapper, 4); // VGPR input val
2998 applyDefaultMapping(OpdMapper);
3008 substituteSimpleCopyRegs(OpdMapper, 2);
3009 substituteSimpleCopyRegs(OpdMapper, 3);
3015 applyMappingBFEIntrinsic(OpdMapper, true);
3018 applyMappingBFEIntrinsic(OpdMapper, false);
3031 applyMappingImage(MI, OpdMapper, MRI, RSrcIntrin->RsrcArg);
3040 assert(OpdMapper.getVRegs(0).empty());
3041 substituteSimpleCopyRegs(OpdMapper, 3);
3049 substituteSimpleCopyRegs(OpdMapper, 1);
3082 applyMappingImage(MI, OpdMapper, MRI, RSrcIntrin->RsrcArg);
3095 if (applyMappingLoad(MI, OpdMapper, MRI))
3100 applyMappingDynStackAlloc(MI, OpdMapper, MRI);
3106 return applyDefaultMapping(OpdMapper);