Target/AMDGPU/AMDGPUISelLowering.h

37   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
40   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
41   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
45   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
46   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
50   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
51   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
52   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
54   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
56   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
60   SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
62   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
64   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
65   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
67   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
69   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
70   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
71   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
72   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
74   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
106                                      SelectionDAG &DAG) const;
110                                               SelectionDAG &DAG) const;
111   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
112   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
117   std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
123                                           SelectionDAG &DAG) const;
126   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
129   SDValue WidenVectorLoad(SDValue Op, SelectionDAG &DAG) const;
132   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
134   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
135   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
136   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
137   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
138   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
174   SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
194   bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
211                       SelectionDAG &DAG) const override;
214                               SelectionDAG &DAG,
225                                   SelectionDAG &DAG) const;
227   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
231                           SelectionDAG &DAG) const override;
249   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
252   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
255   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
259                                   SelectionDAG &DAG) const = 0;
267                                      const SelectionDAG &DAG,
271                                            const SelectionDAG &DAG,
281                                     const SelectionDAG &DAG,
290   SDValue CreateLiveInRegister(SelectionDAG &DAG,
295   SDValue CreateLiveInRegister(SelectionDAG &DAG,
302   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
310   SDValue loadStackInputValue(SelectionDAG &DAG,
315   SDValue storeStackInputValue(SelectionDAG &DAG,
321   SDValue loadInputValue(SelectionDAG &DAG,