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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/

Lines Matching defs:AMDGPUTargetLowering

46 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
55 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
61 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) {
69 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
654 bool AMDGPUTargetLowering::allUsesHaveSourceMods(const SDNode *N,
678 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
689 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
693 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
699 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
707 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
712 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
751 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, EVT CastTy,
776 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
780 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
784 bool AMDGPUTargetLowering::isSDNodeAlwaysUniform(const SDNode * N) const {
814 SDValue AMDGPUTargetLowering::getNegatedExpression(
838 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
846 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
853 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
859 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
871 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
880 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
892 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
902 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
914 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
918 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
1003 void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
1116 SDValue AMDGPUTargetLowering::LowerReturn(
1133 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1138 CCAssignFn *AMDGPUTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1143 SDValue AMDGPUTargetLowering::addTokenForArgument(SDValue Chain,
1179 SDValue AMDGPUTargetLowering::lowerUnhandledCall(CallLoweringInfo &CLI,
1206 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
1211 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1222 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
1263 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
1280 bool AMDGPUTargetLowering::hasDefinedInitializer(const GlobalValue *GV) {
1288 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
1336 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
1356 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
1369 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1443 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1457 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1465 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1477 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const {
1492 AMDGPUTargetLowering::splitVector(const SDValue &N, const SDLoc &DL,
1507 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1568 SDValue AMDGPUTargetLowering::WidenVectorLoad(SDValue Op,
1593 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1637 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1748 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1963 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
2018 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
2079 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
2094 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
2134 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
2183 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2210 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2222 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2251 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2276 SDValue AMDGPUTargetLowering::LowerFLOG(SDValue Op, SelectionDAG &DAG,
2289 SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
2307 SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
2381 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2466 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2489 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2526 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2566 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2595 SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const {
2694 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2717 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2740 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2768   return AMDGPUTargetLowering::numBitsUnsigned(Op, DAG) <= 24;
2775     AMDGPUTargetLowering::numBitsSigned(Op, DAG) < 24;
2838 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const {
2859 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2914 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2972 SDValue AMDGPUTargetLowering::performAssertSZExtCombine(SDNode *N,
2995 SDValue AMDGPUTargetLowering::performIntrinsicWOChainCombine(
3019 SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
3042 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
3110 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
3145 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
3194 SDValue AMDGPUTargetLowering::performTruncateCombine(
3303 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
3350 SDValue AMDGPUTargetLowering::performMulhsCombine(SDNode *N,
3374 SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
3398 SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
3427 SDValue AMDGPUTargetLowering::getFFBX_U32(SelectionDAG &DAG,
3454 SDValue AMDGPUTargetLowering::performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond,
3571 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
3629 bool AMDGPUTargetLowering::isConstantCostlierToNegate(SDValue N) const {
3660 SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
3862 SDValue AMDGPUTargetLowering::performFAbsCombine(SDNode *N,
3887 SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
3899 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
4115 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
4151 SDValue AMDGPUTargetLowering::loadStackInputValue(SelectionDAG &DAG,
4167 SDValue AMDGPUTargetLowering::storeStackInputValue(SelectionDAG &DAG,
4181 SDValue AMDGPUTargetLowering::loadInputValue(SelectionDAG &DAG,
4202 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
4222 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
4376 SDValue AMDGPUTargetLowering::getSqrtEstimate(SDValue Operand,
4394 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
4415 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
4558 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
4600 unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
4623 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
4731 AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {