Lines Matching refs:SDValue
74 static bool isNullConstantOrUndef(SDValue V) {
82 static bool getConstantValue(SDValue N, uint32_t &Out) {
167 std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
168 bool isNoNanSrc(SDValue N) const;
196 SDNode *glueCopyToOp(SDNode *N, SDValue NewChain, SDValue Glue) const;
197 SDNode *glueCopyToM0(SDNode *N, SDValue Val) const;
201 virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
202 virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
203 bool isDSOffsetLegal(SDValue Base, unsigned Offset,
205 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
206 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
207 SDValue &Offset1) const;
208 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
209 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
210 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
211 SDValue &TFE, SDValue &DLC, SDValue &SWZ) const;
212 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
213 SDValue &SOffset, SDValue &Offset, SDValue &GLC,
214 SDValue &SLC, SDValue &TFE, SDValue &DLC,
215 SDValue &SWZ) const;
216 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
217 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
218 SDValue &SLC) const;
220 SDValue Addr, SDValue &RSrc, SDValue &VAddr,
221 SDValue &SOffset, SDValue &ImmOffset) const;
223 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
224 SDValue &Offset) const;
226 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
227 SDValue &Offset, SDValue &GLC, SDValue &SLC,
228 SDValue &TFE, SDValue &DLC, SDValue &SWZ) const;
229 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
230 SDValue &Offset, SDValue &SLC) const;
231 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
232 SDValue &Offset) const;
235 bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr,
236 SDValue &Offset, SDValue &SLC) const;
237 bool SelectFlatAtomic(SDNode *N, SDValue Addr, SDValue &VAddr,
238 SDValue &Offset, SDValue &SLC) const;
239 bool SelectFlatAtomicSigned(SDNode *N, SDValue Addr, SDValue &VAddr,
240 SDValue &Offset, SDValue &SLC) const;
242 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
244 SDValue Expand32BitAddress(SDValue Addr) const;
245 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
247 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
248 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
249 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
250 bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
251 bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
252 bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;
254 bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
255 bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods) const;
256 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
257 bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
258 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
259 SDValue &Clamp, SDValue &Omod) const;
260 bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
261 SDValue &Clamp, SDValue &Omod) const;
263 bool SelectVOP3OMods(SDValue In, SDValue &Src,
264 SDValue &Clamp, SDValue &Omod) const;
266 bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
268 bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;
270 bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
271 bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
272 bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
274 SDValue getHi16Elt(SDValue In) const;
276 SDValue getMaterializedScalarImm32(int64_t Val, const SDLoc &DL) const;
286 SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
310 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
311 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
312 SDValue& Offset);
319 bool SelectADDRIndirect(SDValue Addr, SDValue &Base,
320 SDValue &Offset) override;
321 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
322 SDValue &Offset) override;
333 static SDValue stripBitcast(SDValue Val) {
338 static bool isExtractHiElt(SDValue In, SDValue &Out) {
343 SDValue Srl = In.getOperand(0);
358 static SDValue stripExtractLoElt(SDValue In) {
360 SDValue Src = In.getOperand(0);
415 SDValue Lo = N->getOperand(0);
416 SDValue Hi = N->getOperand(1);
429 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
430 SDValue Ops[] = {
442 SDValue NewLoadHi =
447 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewLoadHi);
448 CurDAG->ReplaceAllUsesOfValueWith(SDValue(LdHi, 1), NewLoadHi.getValue(1));
457 SDValue TiedIn = getHi16Elt(Hi);
472 SDValue Ops[] = {
476 SDValue NewLoadLo =
481 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewLoadLo);
482 CurDAG->ReplaceAllUsesOfValueWith(SDValue(LdLo, 1), NewLoadLo.getValue(1));
517 bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const {
592 SDValue SubRegOp = N->getOperand(OpNo + 1);
600 SDNode *AMDGPUDAGToDAGISel::glueCopyToOp(SDNode *N, SDValue NewChain,
601 SDValue Glue) const {
602 SmallVector <SDValue, 8> Ops;
611 SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N, SDValue Val) const {
617 SDValue M0 = Lowering.copyToM0(*CurDAG, N->getOperand(0), SDLoc(N), Val);
643 const SDValue Ops[] = {
645 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
646 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)};
656 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
669 SmallVector<SDValue, 32 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
695 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
785 SDValue RC, SubReg0, SubReg1;
798 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
931 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
932 SDValue &Offset) {
936 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
937 SDValue &Offset) {
960 SDValue AMDGPUDAGToDAGISel::getMaterializedScalarImm32(int64_t Val,
965 return SDValue(Mov, 0);
971 SDValue LHS = N->getOperand(0);
972 SDValue RHS = N->getOperand(1);
980 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
981 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
1006 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
1009 SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
1012 SDValue AddHiArgs[] = {
1013 SDValue(Hi0, 0),
1014 SDValue(Hi1, 0),
1015 SDValue(AddLo, 1)
1019 SDValue RegSequenceArgs[] = {
1021 SDValue(AddLo,0),
1023 SDValue(AddHi,0),
1031 ReplaceUses(SDValue(N, 1), SDValue(AddHi, 1));
1040 SDValue LHS = N->getOperand(0);
1041 SDValue RHS = N->getOperand(1);
1042 SDValue CI = N->getOperand(2);
1094 SDValue Ops[10];
1108 SDValue Ops[8];
1129 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
1140 SDValue Clamp = CurDAG->getTargetConstant(0, SL, MVT::i1);
1141 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
1146 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(SDValue Base, unsigned Offset,
1161 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
1162 SDValue &Offset) const {
1165 SDValue N0 = Addr.getOperand(0);
1166 SDValue N1 = Addr.getOperand(1);
1179 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
1184 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
1188 SmallVector<SDValue, 3> Opnds;
1203 Base = SDValue(MachineSub, 0);
1218 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
1221 Base = SDValue(MovZero, 0);
1234 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
1235 SDValue &Offset0,
1236 SDValue &Offset1) const {
1240 SDValue N0 = Addr.getOperand(0);
1241 SDValue N1 = Addr.getOperand(1);
1260 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
1265 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
1269 SmallVector<SDValue, 3> Opnds;
1282 Base = SDValue(MachineSub, 0);
1295 SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
1299 Base = SDValue(MovZero, 0);
1314 bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
1315 SDValue &VAddr, SDValue &SOffset,
1316 SDValue &Offset, SDValue &Offen,
1317 SDValue &Idxen, SDValue &Addr64,
1318 SDValue &GLC, SDValue &SLC,
1319 SDValue &TFE, SDValue &DLC,
1320 SDValue &SWZ) const {
1342 SDValue N0 = Addr;
1354 SDValue N2 = N0.getOperand(0);
1355 SDValue N3 = N0.getOperand(1);
1362 Ptr = SDValue(buildSMovImm64(DL, 0, MVT::v2i32), 0);
1378 Ptr = SDValue(buildSMovImm64(DL, 0, MVT::v2i32), 0);
1403 SDValue(CurDAG->getMachineNode(
1410 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1411 SDValue &VAddr, SDValue &SOffset,
1412 SDValue &Offset, SDValue &GLC,
1413 SDValue &SLC, SDValue &TFE,
1414 SDValue &DLC, SDValue &SWZ) const {
1415 SDValue Ptr, Offen, Idxen, Addr64;
1433 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
1440 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
1441 SDValue &VAddr, SDValue &SOffset,
1442 SDValue &Offset,
1443 SDValue &SLC) const {
1445 SDValue GLC, TFE, DLC, SWZ;
1455 std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
1461 SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(),
1476 SDValue Addr, SDValue &Rsrc,
1477 SDValue &VAddr, SDValue &SOffset,
1478 SDValue &ImmOffset) const {
1492 SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
1495 VAddr = SDValue(MovHighBits, 0);
1512 SDValue N0 = Addr.getOperand(0);
1513 SDValue N1 = Addr.getOperand(1);
1547 SDValue Addr,
1548 SDValue &SRsrc,
1549 SDValue &SOffset,
1550 SDValue &Offset) const {
1573 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1574 SDValue &SOffset, SDValue &Offset,
1575 SDValue &GLC, SDValue &SLC,
1576 SDValue &TFE, SDValue &DLC,
1577 SDValue &SWZ) const {
1578 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1596 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1602 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1603 SDValue &Soffset, SDValue &Offset
1605 SDValue GLC, SLC, TFE, DLC, SWZ;
1609 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1610 SDValue &Soffset, SDValue &Offset,
1611 SDValue &SLC) const {
1612 SDValue GLC, TFE, DLC, SWZ;
1620 N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode();
1624 for (SDValue V : N->op_values())
1631 static bool getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr,
1632 SDValue &N0, SDValue &N1) {
1639 SDValue Lo = Addr.getOperand(0).getOperand(0);
1641 SDValue BaseLo = Lo.getOperand(0);
1642 SDValue BaseHi = Addr.getOperand(0).getOperand(1);
1664 SDValue Addr,
1665 SDValue &VAddr,
1666 SDValue &Offset,
1667 SDValue &SLC) const {
1673 SDValue N0, N1;
1725 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
1726 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
1733 SDValue AddOffsetLo =
1735 SDValue AddOffsetHi =
1739 SDValue Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
1743 {AddOffsetLo, SDValue(N0Lo, 0), Clamp});
1747 {AddOffsetHi, SDValue(N0Hi, 0), SDValue(Add, 1), Clamp});
1749 SDValue RegSequenceArgs[] = {
1751 SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1};
1753 Addr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1767 SDValue Addr,
1768 SDValue &VAddr,
1769 SDValue &Offset,
1770 SDValue &SLC) const {
1775 SDValue Addr,
1776 SDValue &VAddr,
1777 SDValue &Offset,
1778 SDValue &SLC) const {
1782 bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
1783 SDValue &Offset, bool &Imm) const {
1826 SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
1827 Offset = SDValue(
1833 SDValue AMDGPUDAGToDAGISel::Expand32BitAddress(SDValue Addr) const {
1843 SDValue AddrHi = CurDAG->getTargetConstant(AddrHiVal, SL, MVT::i32);
1845 const SDValue Ops[] = {
1849 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, AddrHi),
1854 return SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, SL, MVT::i64,
1858 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
1859 SDValue &Offset, bool &Imm) const {
1866 SDValue N0, N1;
1888 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
1889 SDValue &Offset) const {
1894 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
1895 SDValue &Offset) const {
1906 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
1907 SDValue &Offset) const {
1913 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
1914 SDValue &Offset) const {
1927 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
1928 SDValue &Offset) const {
1942 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
1943 SDValue &Base,
1944 SDValue &Offset) const {
1948 SDValue N0 = Index.getOperand(0);
1949 SDValue N1 = Index.getOperand(1);
1973 SDValue Val, uint32_t Offset,
1979 SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);
1989 const SDValue &Shl = N->getOperand(0);
2015 const SDValue &Srl = N->getOperand(0);
2037 const SDValue &And = N->getOperand(0);
2067 SDValue Src = N->getOperand(0);
2090 SDValue Cond = N->getOperand(1);
2112 SDValue Cond = N->getOperand(1);
2142 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32
2152 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
2169 SDValue Src0 = N->getOperand(0);
2170 SDValue Src1 = N->getOperand(1);
2171 SDValue Src2 = N->getOperand(2);
2187 SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32);
2188 SDValue Ops[] = {
2220 SDValue SRsrc, VAddr, SOffset, Offset, SLC;
2225 SDValue CmpVal = Mem->getOperand(2);
2229 SDValue Ops[] = {
2238 SDValue SRsrc, SOffset, Offset, SLC;
2243 SDValue CmpVal = Mem->getOperand(2);
2244 SDValue Ops[] = {
2261 SDValue Extract
2262 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
2264 ReplaceUses(SDValue(N, 0), Extract);
2265 ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
2275 SDValue Chain = N->getOperand(0);
2276 SDValue Ptr = N->getOperand(2);
2281 SDValue Offset;
2283 SDValue PtrBase = Ptr.getOperand(0);
2284 SDValue PtrOffset = Ptr.getOperand(1);
2298 SDValue Ops[] = {
2341 SDValue BaseOffset = N->getOperand(HasVSrc ? 3 : 2);
2374 SDValue(SGPROffset, 0),
2376 glueCopyToM0(N, SDValue(M0Base, 0));
2379 SDValue Chain = N->getOperand(0);
2380 SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32);
2383 SDValue GDS = CurDAG->getTargetConstant(1, SL, MVT::i1);
2386 SmallVector<SDValue, 5> Ops;
2425 SDValue ToM0 = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, AMDGPU::M0,
2426 N->getOperand(5), SDValue());
2445 SDValue(InterpMov, 0), // Src2 - holds two f16 values selected by high
2449 SDValue(InterpMov, 1)
2452 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(InterpP1LV, 0));
2491 SDValue Src = N->getOperand(1);
2513 bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
2531 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
2532 SDValue &SrcMods) const {
2542 bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src,
2543 SDValue &SrcMods) const {
2548 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const {
2556 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
2557 SDValue &SrcMods, SDValue &Clamp,
2558 SDValue &Omod) const {
2566 bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src,
2567 SDValue &Clamp, SDValue &Omod) const {
2577 bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src,
2578 SDValue &SrcMods) const {
2590 SDValue Lo = stripBitcast(Src.getOperand(0));
2591 SDValue Hi = stripBitcast(Src.getOperand(1));
2631 bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src,
2632 SDValue &SrcMods) const {
2639 bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src,
2640 SDValue &SrcMods) const {
2647 bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
2688 bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src,
2689 SDValue &SrcMods) const {
2696 SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
2711 SDValue Src;
2715 return SDValue();
2832 bool R600DAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
2833 SDValue& IntPtr) {
2842 bool R600DAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
2843 SDValue& BaseReg, SDValue &Offset) {
2889 bool R600DAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
2890 SDValue &Offset) {
2913 bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
2914 SDValue &Offset) {