Lines Matching refs:OrigArg
188 const ArgInfo &OrigArg, unsigned OrigArgIdx,
193 LLVMContext &Ctx = OrigArg.Ty->getContext();
195 if (OrigArg.Ty->isVoidTy())
199 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs);
201 assert(OrigArg.Regs.size() == SplitVTs.size());
205 Register Reg = OrigArg.Regs[SplitIdx];
211 if (OrigArg.Flags[0].isSExt()) {
212 assert(OrigArg.Regs.size() == 1 && "expect only simple return values");
214 } else if (OrigArg.Flags[0].isZExt()) {
215 assert(OrigArg.Regs.size() == 1 && "expect only simple return values");
235 SplitArgs.emplace_back(Reg, Ty, OrigArg.Flags, OrigArg.IsFixed);
251 SplitArgs.emplace_back(ArrayRef<Register>(PartReg), PartTy, OrigArg.Flags);
732 ArgInfo OrigArg(VRegs[Idx], Arg.getType());
734 setArgFlags(OrigArg, OrigArgIdx, DL, F);
737 B, OrigArg, OrigArgIdx, SplitArgs, DL, CC,