Lines Matching refs:MCInst
22 #include "llvm/MC/MCInst.h"
56 uint64_t getBinaryCodeForInstr(const MCInst &MI,
62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
76 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
82 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
88 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
101 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
107 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
124 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
130 uint32_t getMoveVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
136 uint32_t getFixedPointScaleOpValue(const MCInst &MI, unsigned OpIdx,
140 uint32_t getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
146 uint32_t getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
149 uint32_t getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
152 uint32_t getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
155 uint32_t getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
158 uint32_t getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
161 uint32_t getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
165 uint32_t getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
168 uint32_t getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
172 unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue,
175 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
179 unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
183 fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
186 unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
192 verifyInstructionPredicates(const MCInst &MI,
201 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
212 AArch64MCCodeEmitter::getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
233 AArch64MCCodeEmitter::getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
259 AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
296 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
317 AArch64MCCodeEmitter::getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
337 AArch64MCCodeEmitter::getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
346 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
366 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
387 AArch64MCCodeEmitter::getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
415 AArch64MCCodeEmitter::getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
440 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
448 AArch64MCCodeEmitter::getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx,
457 AArch64MCCodeEmitter::getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx,
466 AArch64MCCodeEmitter::getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx,
475 AArch64MCCodeEmitter::getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx,
484 AArch64MCCodeEmitter::getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx,
493 AArch64MCCodeEmitter::getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx,
502 AArch64MCCodeEmitter::getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx,
511 AArch64MCCodeEmitter::getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx,
520 AArch64MCCodeEmitter::getImm8OptLsl(const MCInst &MI, unsigned OpIdx,
538 AArch64MCCodeEmitter::getSVEIncDecImm(const MCInst &MI, unsigned OpIdx,
550 const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
560 unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
592 void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
620 AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI,
630 AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI,
640 const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {