Lines Matching refs:DefMI
448 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
449 if (!DefMI->isFullCopy())
451 VReg = DefMI->getOperand(1).getReg();
466 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
469 switch (DefMI->getOpcode()) {
473 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
480 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
481 DefMI->getOperand(3).getImm() != 0)
490 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
501 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
508 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
521 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
3321 bool llvm::isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
3324 return any_of(instructionsWithoutDebug(std::next(DefMI.getIterator()),
5506 MachineInstr *DefMI = MRI->getVRegDef(VReg);
5509 while (DefMI->isCopy()) {
5510 Register CopyVReg = DefMI->getOperand(1).getReg();
5515 DefMI = MRI->getVRegDef(CopyVReg);
5518 switch (DefMI->getOpcode()) {
5526 if (DefMI->getParent() != MBB)
5531 bool Is32Bit = (DefMI->getOpcode() == AArch64::ANDWri);
5533 DefMI->getOperand(2).getImm(), Is32Bit ? 32 : 64);
5537 MachineOperand &MO = DefMI->getOperand(1);
5571 if (!(DefMI->getOperand(1).getReg() == AArch64::WZR &&
5572 DefMI->getOperand(2).getReg() == AArch64::WZR) &&
5573 !(DefMI->getOperand(1).getReg() == AArch64::XZR &&
5574 DefMI->getOperand(2).getReg() == AArch64::XZR))
5577 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
5580 AArch64CC::CondCode CC = (AArch64CC::CondCode)DefMI->getOperand(3).getImm();
5584 if (areCFlagsAccessedBetweenInstrs(DefMI, MI, &getRegisterInfo(), AK_Write))