Lines Matching defs:MIB
409 const MachineInstrBuilder MIB =
412 MIB.addImm(Cond[3].getImm());
413 MIB.addMBB(TBB);
2595 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
2600 return MIB.addReg(Reg, State);
2603 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
2604 return MIB.addReg(Reg, State, SubIdx);
2634 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2635 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
2636 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
2637 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
2658 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2659 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
2660 MIB.addReg(ZeroReg);
2661 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
2662 MIB.addImm(0);
4436 MachineInstrBuilder MIB;
4438 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4443 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4449 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4456 InsInstrs.push_back(MIB);
4480 MachineInstrBuilder MIB =
4483 InsInstrs.push_back(MIB);
4576 MachineInstrBuilder MIB =
4582 InsInstrs.push_back(MIB);