Lines Matching refs:NewOp
7955 static SDValue tryAdvSIMDModImm64(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
7966 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
7976 static SDValue tryAdvSIMDModImm32(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
8008 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS,
8012 Mov = DAG.getNode(NewOp, dl, MovTy,
8024 static SDValue tryAdvSIMDModImm16(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
8048 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS,
8052 Mov = DAG.getNode(NewOp, dl, MovTy,
8064 static SDValue tryAdvSIMDModImm321s(unsigned NewOp, SDValue Op,
8084 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
8095 static SDValue tryAdvSIMDModImm8(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
8106 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
8116 static SDValue tryAdvSIMDModImmFP(unsigned NewOp, SDValue Op, SelectionDAG &DAG,
8137 SDValue Mov = DAG.getNode(NewOp, dl, MovTy,
8290 SDValue NewOp;
8292 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
8294 (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
8296 return NewOp;
8298 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::ORRi, Op, DAG,
8300 (NewOp = tryAdvSIMDModImm16(AArch64ISD::ORRi, Op, DAG,
8302 return NewOp;
8349 SDValue NewOp;
8350 if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
8351 (NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
8352 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
8353 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
8354 (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
8355 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
8356 return NewOp;
8359 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
8360 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
8361 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
8362 return NewOp;
8365 if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
8366 (NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
8367 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
8368 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
8369 (NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
8370 (NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
8371 return NewOp;
8374 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
8375 (NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
8376 (NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
8377 return NewOp;
11110 SDValue NewOp;
11113 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG,
11115 (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG,
11117 return NewOp;
11120 if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::BICi, SDValue(N, 0), DAG,
11122 (NewOp = tryAdvSIMDModImm16(AArch64ISD::BICi, SDValue(N, 0), DAG,
11124 return NewOp;
12685 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
12686 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
15167 unsigned NewOp) const {
15188 auto ScalableRes = DAG.getNode(NewOp, DL, ContainerVT, Operands);
15201 return DAG.getNode(NewOp, DL, VT, Operands);