Lines Matching refs:Add
177 // Add legal sve predicate types
183 // Add legal sve data types
374 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
417 // Custom lower Add/Sub/Mul with overflow.
918 // FIXME: Add custom lowering of MLOAD to handle different passthrus (not a
2447 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
2453 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
2460 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
4277 // Add a chain value for each stack argument corresponding
4691 // Add argument registers to the end of the list so that they are known live
4697 // Add a register mask operand representing the call-preserved registers.
4874 // Add the flag if we have it.
5336 // Add the offset from the start of the .tls section (section base).
7020 // Add this element source to the list if it's not already there.
7850 // TODO: Add special case for constant false
9764 case Instruction::Add: {
10472 // Add (N0 < 0) ? Pow2 - 1 : 0;
10475 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
10476 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
10479 Created.push_back(Add.getNode());