Lines Matching defs:Op0IsKill
238 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
256 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
258 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
260 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
262 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
266 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
270 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1081 /*Op0IsKill=*/false, Addr.getShift(),
1085 /*Op0IsKill=*/false, Addr.getShift(),
1089 /*Op0IsKill=*/false, Addr.getShift());
1563 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,
1567 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1569 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1578 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
3674 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
3676 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
4045 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
4061 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
4065 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
4071 Op0, Op0IsKill, Op1, Op1IsKill,
4075 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
4081 Op0, Op0IsKill, Op1, Op1IsKill,
4085 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4104 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4112 bool Op0IsKill, uint64_t Shift,
4135 .addReg(Op0, getKillRegState(Op0IsKill));
4183 .addReg(Op0, getKillRegState(Op0IsKill))
4186 Op0IsKill = true;
4188 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4191 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4207 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
4209 Op0IsKill = Op1IsKill = true;
4211 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4219 bool Op0IsKill, uint64_t Shift,
4242 .addReg(Op0, getKillRegState(Op0IsKill));
4286 Op0IsKill = true;
4304 .addReg(Op0, getKillRegState(Op0IsKill))
4307 Op0IsKill = true;
4309 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4312 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4330 Op0IsKill = Op1IsKill = true;
4332 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4340 bool Op0IsKill, uint64_t Shift,
4363 .addReg(Op0, getKillRegState(Op0IsKill));
4413 .addReg(Op0, getKillRegState(Op0IsKill))
4416 Op0IsKill = true;
4418 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4794 bool Op0IsKill = hasTrivialKill(Op0);
4799 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4802 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4805 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4818 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4829 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4832 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4835 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4877 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4878 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);