Lines Matching defs:IsZExt
203 bool WantResult = true, bool IsZExt = false);
223 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
237 bool IsZExt = false);
241 bool IsZExt = false);
265 uint64_t Imm, bool IsZExt = true);
269 uint64_t Imm, bool IsZExt = true);
273 uint64_t Imm, bool IsZExt = false);
313 bool IsZExt = isa<ZExtInst>(I);
320 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
1082 /*IsZExt=*/true);
1086 /*IsZExt=*/false);
1160 bool WantResult, bool IsZExt) {
1171 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1175 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1208 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1212 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1483 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1498 return emitICmp(VT, LHS, RHS, IsZExt);
1506 bool IsZExt) {
1508 IsZExt) != 0;
1553 bool SetFlags, bool WantResult, bool IsZExt) {
1555 IsZExt);
1583 bool SetFlags, bool WantResult, bool IsZExt) {
1585 IsZExt);
3920 bool IsZExt = Outs[0].Flags.isZExt();
3921 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
4012 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
4020 if (IsZExt) {
4113 bool IsZExt) {
4138 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4177 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4220 bool IsZExt) {
4245 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4277 if (Shift >= SrcBits && IsZExt)
4282 if (!IsZExt) {
4283 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4289 IsZExt = true;
4298 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4341 bool IsZExt) {
4366 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4398 if (Shift >= SrcBits && IsZExt)
4407 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4422 bool IsZExt) {
4442 return emiti1Ext(SrcReg, DestVT, IsZExt);
4445 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4447 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4452 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4454 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4459 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4547 bool IsZExt = isa<ZExtInst>(I);
4555 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
4564 if (IsZExt) {
4605 bool IsZExt = isa<ZExtInst>(I);
4607 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
4630 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4703 bool IsZExt = true;
4709 IsZExt = true;
4718 IsZExt = false;
4730 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);
4769 bool IsZExt = I->getOpcode() != Instruction::AShr;
4776 IsZExt = true;
4785 IsZExt = false;
4799 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4802 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4805 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);