Lines Matching defs:IR
40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
42 Resources->canBeDispatched(IR.getInstruction()->getUsedBuffers());
55 LSUnit::Status LSS = LSU.isAvailable(IR);
71 InstRef &IR,
73 Instruction *IS = IR.getInstruction();
82 IS->execute(IR.getSourceIndex());
87 LSU.onInstructionIssued(IR);
93 IssuedSet.emplace_back(IR);
95 LSU.onInstructionExecuted(IR);
100 InstRef &IR,
104 const Instruction &Inst = *IR.getInstruction();
106 HasDependentUsers |= Inst.isMemOp() && LSU.hasDependentUsers(IR);
109 issueInstructionImpl(IR, UsedResources);
124 InstRef &IR = *I;
125 if (!IR)
129 Instruction &IS = *IR.getInstruction();
135 if (IS.isMemOp() && !LSU.isReady(IR)) {
140 LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
143 Ready.emplace_back(IR);
144 ReadySet.emplace_back(IR);
146 IR.invalidate();
160 InstRef &IR = *I;
161 if (!IR)
166 Instruction &IS = *IR.getInstruction();
172 if (IS.isMemOp() && LSU.isWaiting(IR)) {
177 LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
180 Pending.emplace_back(IR);
181 PendingSet.emplace_back(IR);
183 IR.invalidate();
195 InstRef &IR = ReadySet[I];
197 Strategy->compare(IR, ReadySet[QueueIndex])) {
198 Instruction &IS = *IR.getInstruction();
212 InstRef IR = ReadySet[QueueIndex];
215 return IR;
221 InstRef &IR = *I;
222 if (!IR)
224 Instruction &IS = *IR.getInstruction();
226 LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << IR
232 // Instruction IR has completed execution.
233 LSU.onInstructionExecuted(IR);
234 Executed.emplace_back(IR);
236 IR.invalidate();
251 for (const InstRef &IR : make_range(PendingSet.begin(), EndIt)) {
252 const Instruction &IS = *IR.getInstruction();
256 if (IS.isMemOp() && LSU.isPending(IR))
257 MemDeps.emplace_back(IR);
260 RegDeps.emplace_back(IR);
273 for (InstRef &IR : IssuedSet)
274 IR.getInstruction()->cycleEvent();
277 for (InstRef &IR : PendingSet)
278 IR.getInstruction()->cycleEvent();
280 for (InstRef &IR : WaitSet)
281 IR.getInstruction()->cycleEvent();
290 bool Scheduler::mustIssueImmediately(const InstRef &IR) const {
291 const InstrDesc &Desc = IR.getInstruction()->getDesc();
300 bool Scheduler::dispatch(InstRef &IR) {
301 Instruction &IS = *IR.getInstruction();
306 IS.setLSUTokenID(LSU.dispatch(IR));
308 if (IS.isDispatched() || (IS.isMemOp() && LSU.isWaiting(IR))) {
309 LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
310 WaitSet.push_back(IR);
314 if (IS.isPending() || (IS.isMemOp() && LSU.isPending(IR))) {
315 LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR
317 PendingSet.push_back(IR);
322 assert(IS.isReady() && (!IS.isMemOp() || LSU.isReady(IR)) &&
332 if (!mustIssueImmediately(IR)) {
333 LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the ReadySet\n");
334 ReadySet.push_back(IR);