Lines Matching refs:Op0
744 SDValue Op0 = Op.getOperand(0);
747 DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
750 return Op0;
755 SDValue Op0 = Op.getOperand(0);
762 Op0.getScalarValueSizeInBits() == BitWidth &&
763 getBooleanContents(Op0.getValueType()) ==
771 return Op0;
777 SDValue Op0 = Op.getOperand(0);
781 return Op0;
783 unsigned NumSignBits = DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
785 return Op0;
1136 SDValue Op0 = Op.getOperand(0);
1142 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedLHS, Known2, TLO,
1158 Op0, DemandedBits, DemandedLHS, TLO.DAG, Depth + 1);
1162 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1164 SDValue NewOp = TLO.DAG.getVectorShuffle(VT, dl, Op0, Op1, ShuffleMask);
1171 SDValue Op0 = Op.getOperand(0);
1180 KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
1184 return TLO.CombineTo(Op, Op0);
1197 if (isBitwiseNot(Op0) && Op0.hasOneUse() &&
1199 SDValue Xor = TLO.DAG.getNode(ISD::XOR, dl, VT, Op0.getOperand(0), Op1);
1208 if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
1216 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1220 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1222 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1230 return TLO.CombineTo(Op, Op0);
1248 SDValue Op0 = Op.getOperand(0);
1255 if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts,
1263 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1267 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1269 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1277 return TLO.CombineTo(Op, Op0);
1291 SDValue Op0 = Op.getOperand(0);
1298 if (SimplifyDemandedBits(Op0, DemandedBits, DemandedElts, Known2, TLO,
1306 Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
1310 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1312 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1320 return TLO.CombineTo(Op, Op0);
1331 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, VT, Op0, Op1));
1343 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op0, ANDC));
1352 SDValue New = TLO.DAG.getNOT(dl, Op0, VT);
1402 SDValue Op0 = Op.getOperand(0);
1409 Op0.getScalarValueSizeInBits() == BitWidth &&
1410 getBooleanContents(Op0.getValueType()) ==
1418 return TLO.CombineTo(Op, Op0);
1423 if (getBooleanContents(Op0.getValueType()) ==
1430 SDValue Op0 = Op.getOperand(0);
1438 return TLO.CombineTo(Op, Op0);
1444 if (Op0.getOpcode() == ISD::SRL) {
1447 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) {
1457 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1465 if (Op0.getOpcode() == ISD::ANY_EXTEND) {
1466 SDValue InnerOp = Op0.getOperand(0);
1487 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
1508 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1530 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
1533 return TLO.CombineTo(Op, Op0);
1538 SDValue Op0 = Op.getOperand(0);
1546 return TLO.CombineTo(Op, Op0);
1552 if (Op0.getOpcode() == ISD::SHL) {
1555 TLO.DAG.getValidShiftAmountConstant(Op0, DemandedElts)) {
1565 Op, TLO.DAG.getNode(Opc, dl, VT, Op0.getOperand(0), NewSA));
1578 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1590 SDValue Op0 = Op.getOperand(0);
1597 if (TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1) >=
1599 return TLO.CombineTo(Op, Op0);
1606 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1));
1612 return TLO.CombineTo(Op, Op0);
1626 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1640 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags));
1647 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA));
1657 Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1);
1668 SDValue Op0 = Op.getOperand(0);
1679 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1, DemandedBits, DemandedElts,
1685 // fshl: (Op0 << Amt) | (Op1 >> (BW - Amt))
1686 // fshr: (Op0 << (BW - Amt)) | (Op1 >> Amt)
1689 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
1715 SDValue Op0 = Op.getOperand(0);
1719 if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1))
1720 return TLO.CombineTo(Op, Op0);
1752 SDValue Op0 = Op.getOperand(0);
1759 TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1);
1773 TLO.DAG.getNode(ISD::SHL, dl, VT, Op0, ShiftAmt));
1779 return TLO.CombineTo(Op, Op0);
1787 if (SimplifyDemandedBits(Op0, InputDemandedBits, Known, TLO, Depth + 1))
1796 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT));
2147 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
2151 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, Known2, TLO,
2163 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
2172 Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1);
2178 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
2181 TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
2200 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags);
2351 auto SimplifyDemandedVectorEltsBinOp = [&](SDValue Op0, SDValue Op1) {
2352 SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts,
2358 Opcode, SDLoc(Op), VT, NewOp0 ? NewOp0 : Op0, NewOp1 ? NewOp1 : Op1);
2754 SDValue Op0 = Op.getOperand(0);
2762 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
2772 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
2781 SDValue Op0 = Op.getOperand(0);
2789 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
2799 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
2805 SDValue Op0 = Op.getOperand(0);
2812 if (SimplifyDemandedVectorElts(Op0, DemandedElts, KnownUndef, KnownZero,
2827 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
3727 SDValue Op0 = N0;
3728 if (Op0.getOpcode() == ISD::TRUNCATE)
3729 Op0 = Op0.getOperand(0);
3731 if ((Op0.getOpcode() == ISD::XOR) &&
3732 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
3733 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
3734 SDValue XorLHS = Op0.getOperand(0);
3735 SDValue XorRHS = Op0.getOperand(1);
3737 if (Op0.getValueType() == MVT::i1 ||
3747 if (Op0.getOpcode() == ISD::AND &&
3748 isa<ConstantSDNode>(Op0.getOperand(1)) &&
3749 cast<ConstantSDNode>(Op0.getOperand(1))->isOne()) {
3751 if (Op0.getValueType().bitsGT(VT))
3752 Op0 = DAG.getNode(ISD::AND, dl, VT,
3753 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
3755 else if (Op0.getValueType().bitsLT(VT))
3756 Op0 = DAG.getNode(ISD::AND, dl, VT,
3757 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
3760 return DAG.getSetCC(dl, VT, Op0,
3761 DAG.getConstant(0, dl, Op0.getValueType()),
3764 if (Op0.getOpcode() == ISD::AssertZext &&
3765 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
3766 return DAG.getSetCC(dl, VT, Op0,
3767 DAG.getConstant(0, dl, Op0.getValueType()),
4856 SDValue Op0 = N->getOperand(0);
4898 SDValue Res = Op0;
5372 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5373 Created.push_back(Op0.getNode());
5384 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5385 Created.push_back(Op0.getNode());
5390 DAG.getSetCC(DL, SETCCVT, Op0, QVal,
5614 SDValue Op0 = DAG.getNode(ISD::MUL, DL, VT, N, PVal);
5615 Created.push_back(Op0.getNode());
5623 Op0 = DAG.getNode(ISD::ADD, DL, VT, Op0, AVal);
5624 Created.push_back(Op0.getNode());
5636 Op0 = DAG.getNode(ISD::ROTR, DL, VT, Op0, KVal, Flags);
5637 Created.push_back(Op0.getNode());
5642 DAG.getSetCC(DL, SETCCVT, Op0, QVal,
6218 SDValue Op0 = Node->getOperand(0);
6232 Result = DAG.getNode(RevRot, DL, VT, Op0, Sub);
6253 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0),
6254 DAG.getNode(HsOpc, DL, VT, Op0, And1));