Lines Matching refs:IdxVal
1147 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1150 DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorNumElements(), dl));
1168 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
1171 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1172 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
1450 unsigned IdxVal = CIdx->getZExtValue();
1452 if (IdxVal < LoNumElts)
1457 DAG.getVectorIdxConstant(IdxVal - LoNumElts, dl));
2209 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2211 if (IdxVal < LoElts) {
2212 assert(IdxVal + SubVT.getVectorMinNumElements() <= LoElts &&
2217 DAG.getVectorIdxConstant(IdxVal - LoElts, dl));
2227 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2234 if (IdxVal < LoElts)
2237 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
3701 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3702 if (IdxVal == 0 && InVT == WidenVT)
3707 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
3718 DAG.getVectorIdxConstant(IdxVal + i, dl));