Lines Matching refs:ops
86 STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops");
860 for (const SDValue &Op : N->ops())
2171 // fold vector ops
2430 // fold vector ops
3056 // fold vector ops
3382 // fold vector ops
3541 // fold vector ops
3618 // having the target set a limit on number of ops and making a
3841 // fold vector ops
3917 // fold (sdiv X, pow2) -> simple ops after legalize
3986 // fold vector ops
4272 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4280 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4290 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4300 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4420 // fold vector ops
4535 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
5255 // fold vector ops
5949 // fold vector ops
6525 // can be broken down (ie if InstCombine merged two shl or srl ops into a
7275 // fold vector ops
7545 // Logic ops are commutative, so check each operand for a match.
7746 // fold vector ops
8079 // fold vector ops
8268 // fold vector ops
9275 // ...but that only makes sense if a vselect is slower than 2 logic ops, so
9843 // We only do this transform before legal ops because the pattern may be
10770 // In rare cases, there are trivial arithmetic ops in source operands. Sink
10771 // this assert down to source operands so that those arithmetic ops could be
11595 // scalar type is legal. Only do this before legalize ops, since the target
12621 // fold vector ops
12801 // fold vector ops
12881 // fold vector ops
13223 // fold vector ops
14330 // 4) All uses are load / store ops that use it as old base ptr.
14567 // 1) All uses are load / store ops that use it as base ptr (and
16174 // which always true for nonvolatile ops. TODO: Expand
16242 for (SDValue Op : N->ops())
17035 // Try transforming a pair floating point load / store ops to integer
17036 // load / store ops.
17384 for (SDValue Op : reverse(ArgVal->ops())) {
18749 for (const SDValue &Op : N->ops()) {
18810 for (SDValue Op : N->ops()) {
18895 for (SDValue Op : N->ops()) {
19009 if (llvm::all_of(N->ops(), IsBuildVectorOrUndef)) {
19018 for (const SDValue &Op : N->ops())
19027 for (const SDValue &Op : N->ops()) {
19224 // for concat ops. The narrow binop alone makes this transform profitable.
19249 // target has temptingly almost legal versions of bitwise logic ops in 256-bit
19483 V->ops().slice(IdxVal, NumElems));
19521 /// followed by concatenation. Narrow vector ops may have better performance
19522 /// than wide ops, and this can unlock further narrowing of other vector ops.
20781 count_if(N0->ops(), [](SDValue V) { return !V.isUndef(); }) == 1 &&
20782 count_if(N1->ops(), [](SDValue V) { return !V.isUndef(); }) == 1) {
20817 // restrict ops like integer div that have immediate UB (eg, div-by-zero)
20862 // The following pattern is likely to emerge with vector reduction ops. Moving
20895 // The following pattern is likely to emerge with vector reduction ops. Moving
22046 // If the chain has more than one use, then we can't reorder the mem ops.
22120 for (const SDValue &Op : TF->ops())