Lines Matching refs:DefSU
311 SUnit *DefSU = I->SU;
312 if (DefSU == &ExitSU)
314 if (DefSU != SU &&
316 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
320 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
321 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);
322 DefSU->addPred(Dep);
480 SUnit *DefSU = V2SU.SU;
486 if (DefSU == SU)
490 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
491 DefSU->addPred(Dep);
501 CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, DefSU));