Lines Matching refs:Def
181 /// Track Def -> Use info used for rewriting copies.
255 RegSubRegPair Def, RewriteMapTy &RewriteMap);
367 const MachineInstr *Def = nullptr;
369 /// The index of the definition in Def.
423 Def = MRI.getVRegDef(Reg);
654 /// retrieve all Def -> Use along the way up to the next source. Any found
694 // Insert the Def -> Use entry for the recently found source.
1107 /// Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
1109 /// multiple sources for a given \p Def are found along the way, we found a
1115 RegSubRegPair Def,
1118 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
1219 /// Rewrite the source found through \p Def, by using the \p RewriteMap
1226 RegSubRegPair Def, RewriteMapTy &RewriteMap) {
1227 assert(!Register::isPhysicalRegister(Def.Reg) &&
1231 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
1234 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1242 if (Def.SubReg) {
1243 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1250 MRI->replaceRegWith(Def.Reg, NewVReg);
1281 RegSubRegPair Def;
1283 while (CpyRewriter.getNextRewritableSource(Src, Def)) {
1286 if (Register::isPhysicalRegister(Def.Reg))
1291 if (!findNextSource(Def, RewriteMap))
1294 RewritePairs.push_back(Def);
1298 for (const RegSubRegPair &Def : RewritePairs) {
1300 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap);
1669 const auto &Def = NAPhysToVirtMIs.find(Reg);
1670 if (Def != NAPhysToVirtMIs.end()) {
1675 NAPhysToVirtMIs.erase(Def);
1681 unsigned Def = RegMI.first;
1682 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1685 NAPhysToVirtMIs.erase(Def);
1814 assert(Def->isCopy() && "Invalid definition");
1815 // Copy instruction are supposed to be: Def = Src.
1819 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 &&
1821 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed");
1823 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1828 const MachineOperand &Src = Def->getOperand(1);
1835 assert(Def->isBitcast() && "Invalid definition");
1838 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects())
1842 if (Def->getDesc().getNumDefs() != 1)
1844 const MachineOperand DefOp = Def->getOperand(DefIdx);
1850 unsigned SrcIdx = Def->getNumOperands();
1853 const MachineOperand &MO = Def->getOperand(OpIdx);
1866 // In some rare case, Def has no input, SrcIdx is out of bound,
1868 if (SrcIdx >= Def->getNumOperands())
1878 const MachineOperand &Src = Def->getOperand(SrcIdx);
1885 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1888 if (Def->getOperand(DefIdx).getSubReg())
1890 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1894 // Def.sub0 =
1895 // Def.sub1 =
1896 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1897 // Def. Thus, it must not be generated.
1899 // Def.sub0 (i.e, not defining the other subregs) and we would
1911 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1915 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1929 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1932 if (Def->getOperand(DefIdx).getSubReg())
1945 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1949 // Def = INSERT_SUBREG v0, v1, sub1
1961 const MachineOperand &MODef = Def->getOperand(DefIdx);
1962 // If the result register (Def) and the base register (v0) do not
1977 // we used for Def.
1982 assert((Def->isExtractSubreg() ||
1983 Def->isExtractSubregLike()) && "Invalid definition");
1985 // Def = EXTRACT_SUBREG v0, sub0
1998 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
2011 assert(Def->isSubregToReg() && "Invalid definition");
2013 // Def = SUBREG_TO_REG Imm, v0, sub0
2019 if (DefSubReg != Def->getOperand(3).getImm())
2023 if (Def->getOperand(2).getSubReg())
2026 return ValueTrackerResult(Def->getOperand(2).getReg(),
2027 Def->getOperand(3).getImm());
2032 assert(Def->isPHI() && "Invalid definition");
2037 if (Def->getOperand(0).getSubReg() != DefSubReg)
2041 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
2042 const MachineOperand &MO = Def->getOperand(i);
2055 assert(Def && "This method needs a valid definition");
2057 assert(((Def->getOperand(DefIdx).isDef() &&
2058 (DefIdx < Def->getDesc().getNumDefs() ||
2059 Def->getDesc().isVariadic())) ||
2060 Def->getOperand(DefIdx).isImplicit()) &&
2062 if (Def->isCopy())
2064 if (Def->isBitcast())
2070 if (Def->isRegSequence() || Def->isRegSequenceLike())
2072 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
2074 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
2076 if (Def->isSubregToReg())
2078 if (Def->isPHI())
2086 if (!Def)
2099 Res.setInst(Def);
2106 Def = DI->getParent();
2110 Def = nullptr;
2118 Def = nullptr;