Lines Matching defs:Ops
490 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
493 assert(Ops.size() == Indices.size() && "incompatible args");
494 assert(!Ops.empty() && "invalid trivial sequence");
499 for (auto Op : Ops)
504 LLT OpTy = getMRI()->getType(Ops[0]);
507 for (unsigned i = 0; i < Ops.size(); ++i) {
508 if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
514 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
515 buildMerge(Res, Ops);
522 for (unsigned i = 0; i < Ops.size(); ++i) {
523 Register ResOut = i + 1 == Ops.size()
526 buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
536 ArrayRef<Register> Ops) {
540 SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
547 std::initializer_list<SrcOp> Ops) {
548 assert(Ops.size() > 1);
549 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, Ops);
582 ArrayRef<Register> Ops) {
586 SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
598 ArrayRef<Register> Ops) {
602 SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
607 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
611 SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());