Lines Matching defs:WideTy
1240 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1243 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1254 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1257 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1272 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1275 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1326 LLT WideTy) {
1339 const int WideSize = WideTy.getSizeInBits();
1348 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1356 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1358 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1359 MRI.createGenericVirtualRegister(WideTy);
1361 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1362 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1429 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1448 LLT WideTy) {
1463 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) {
1476 // Widen SrcTy to WideTy. This does not affect the result, but since the
1479 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1480 SrcTy = WideTy;
1481 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0);
1500 LLT LCMTy = getLCMType(SrcTy, WideTy);
1513 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);
1528 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
1552 LLT WideTy) {
1583 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1590 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1591 Src = MIRBuilder.buildAnyExt(WideTy, Src);
1592 ShiftTy = WideTy;
1593 } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1605 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1620 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1622 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1624 widenScalarDst(MI, WideTy.getScalarType(), 0);
1631 LLT WideTy) {
1635 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1636 widenScalarDst(MI, WideTy);
1643 LLT WideTy) {
1657 unsigned NewBits = WideTy.getScalarSizeInBits();
1660 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1));
1661 auto RHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2));
1662 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount);
1663 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK);
1664 auto ShiftR = MIRBuilder.buildShl(WideTy, RHS, ShiftK);
1666 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy},
1671 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK)
1672 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK);
1680 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1685 return widenScalarExtract(MI, TypeIdx, WideTy);
1687 return widenScalarInsert(MI, TypeIdx, WideTy);
1689 return widenScalarMergeValues(MI, TypeIdx, WideTy);
1691 return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1696 auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
1697 auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
1702 auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1705 APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
1707 WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
1719 return widenScalarAddSubSat(MI, TypeIdx, WideTy);
1727 widenScalarDst(MI, WideTy, 0);
1735 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1742 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1744 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1748 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1753 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1755 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff));
1766 Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1767 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1768 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1769 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1776 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1789 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1791 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1792 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1796 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1797 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1804 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1805 widenScalarDst(MI, WideTy);
1819 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1820 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1821 widenScalarDst(MI, WideTy);
1829 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1830 widenScalarDst(MI, WideTy);
1835 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1846 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1847 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1848 widenScalarDst(MI, WideTy);
1860 widenScalarSrc(MI, WideTy, 1, CvtOp);
1861 widenScalarDst(MI, WideTy);
1866 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1876 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1877 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1878 widenScalarDst(MI, WideTy);
1888 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1889 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1890 widenScalarDst(MI, WideTy);
1894 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1904 widenScalarDst(MI, WideTy);
1906 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1914 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1922 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1930 widenScalarDst(MI, WideTy);
1946 widenScalarSrc(MI, WideTy, 0, ExtType);
1961 ? SrcVal.sext(WideTy.getSizeInBits())
1962 : SrcVal.zext(WideTy.getSizeInBits());
1966 widenScalarDst(MI, WideTy);
1975 switch (WideTy.getSizeInBits()) {
1993 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1999 widenScalarDst(MI, WideTy);
2005 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
2012 widenScalarDst(MI, WideTy);
2014 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
2015 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
2023 widenScalarDst(MI, WideTy);
2029 widenScalarSrc(MI, WideTy, 2, ExtOpcode);
2030 widenScalarSrc(MI, WideTy, 3, ExtOpcode);
2038 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
2049 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
2054 widenScalarDst(MI, WideTy);
2065 WideTy.getSizeInBits()),
2068 widenScalarDst(MI, WideTy, 0);
2077 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
2087 LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
2090 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
2099 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
2141 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
2143 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
2151 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
2159 widenScalarDst(MI, WideTy, 0);
2165 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
2175 widenScalarDst(MI, WideTy, 0);
2186 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
2187 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
2194 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
4991 LLT WideTy = LLT::scalar(DstTy.getSizeInBits());
4992 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0);
4998 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
5000 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
5001 MRI.createGenericVirtualRegister(WideTy);
5003 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
5004 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);