Lines Matching refs:OpInfo
63 void update(const TargetLowering::AsmOperandInfo &OpInfo) {
68 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
69 OpInfo.ConstraintType == TargetLowering::C_Other) {
70 if (OpInfo.Type == InlineAsm::isInput)
72 else if (OpInfo.Type == InlineAsm::isOutput)
74 else if (OpInfo.Type == InlineAsm::isClobber)
87 GISelAsmOperandInfo &OpInfo,
94 if (OpInfo.ConstraintType == TargetLowering::C_Memory)
109 if (OpInfo.isMatchingInputConstraint())
114 if (OpInfo.ConstraintVT != MVT::Other)
116 TLI.getNumRegisters(MF.getFunction().getContext(), OpInfo.ConstraintVT);
137 OpInfo.Regs.push_back(R);
158 static void chooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
160 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
166 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
168 TLI->getConstraintType(OpInfo.Codes[i]);
171 if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory ||
182 assert(OpInfo.Codes[i].size() == 1 &&
189 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
201 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
202 OpInfo.ConstraintType = BestType;
206 TargetLowering::AsmOperandInfo &OpInfo) {
207 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
210 if (OpInfo.Codes.size() == 1) {
211 OpInfo.ConstraintCode = OpInfo.Codes[0];
212 OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode);
214 chooseConstraint(OpInfo, TLI);
218 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
222 Value *Val = OpInfo.CallOperandVal;
228 if (const char *Repl = TLI->LowerXConstraint(OpInfo.ConstraintVT)) {
229 OpInfo.ConstraintCode = Repl;
230 OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode);
297 GISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
300 if (OpInfo.Type == InlineAsm::isInput ||
301 (OpInfo.Type == InlineAsm::isOutput && OpInfo.isIndirect)) {
303 OpInfo.CallOperandVal = const_cast<Value *>(Call.getArgOperand(ArgNo++));
305 if (isa<BasicBlock>(OpInfo.CallOperandVal)) {
310 Type *OpTy = OpInfo.CallOperandVal->getType();
314 if (OpInfo.isIndirect) {
328 OpInfo.ConstraintVT = TLI->getValueType(DL, OpTy, true).getSimpleVT();
330 } else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
333 OpInfo.ConstraintVT =
337 OpInfo.ConstraintVT = TLI->getSimpleValueType(DL, Call.getType());
341 OpInfo.ConstraintVT = MVT::Other;
345 computeConstraintToUse(TLI, OpInfo);
348 ExtraInfo.update(OpInfo);
365 for (auto &OpInfo : ConstraintOperands) {
367 OpInfo.isMatchingInputConstraint()
368 ? ConstraintOperands[OpInfo.getMatchedOperand()]
369 : OpInfo;
372 getRegistersForValue(MF, MIRBuilder, OpInfo, RefOpInfo);
374 switch (OpInfo.Type) {
376 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
378 TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
388 GetOrCreateVRegs(*OpInfo.CallOperandVal);
396 assert(OpInfo.ConstraintType == TargetLowering::C_Register ||
397 OpInfo.ConstraintType == TargetLowering::C_RegisterClass);
399 if (OpInfo.Regs.empty()) {
408 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
410 OpInfo.Regs.size());
411 if (OpInfo.Regs.front().isVirtual()) {
416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
422 for (Register Reg : OpInfo.Regs) {
425 (OpInfo.isEarlyClobber ? RegState::EarlyClobber : 0));
429 OutputOperands.push_back(OpInfo);
434 if (OpInfo.isMatchingInputConstraint()) {
435 unsigned DefIdx = OpInfo.getMatchedOperand();
458 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
479 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
480 OpInfo.isIndirect) {
486 if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
487 OpInfo.ConstraintType == TargetLowering::C_Other) {
490 if (!lowerAsmOperandForConstraint(OpInfo.CallOperandVal,
491 OpInfo.ConstraintCode, Ops,
494 << OpInfo.ConstraintCode << " yet\n");
509 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
511 if (!OpInfo.isIndirect) {
517 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
520 TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
525 GetOrCreateVRegs(*OpInfo.CallOperandVal);
533 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
534 OpInfo.ConstraintType == TargetLowering::C_Register) &&
537 if (OpInfo.isIndirect) {
540 << OpInfo.ConstraintCode << "'\n");
545 if (OpInfo.Regs.empty()) {
552 unsigned NumRegs = OpInfo.Regs.size();
553 ArrayRef<Register> SourceRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
566 if (!buildAnyextOrCopy(OpInfo.Regs[0], SourceRegs[0], MIRBuilder))
568 Inst.addReg(OpInfo.Regs[0]);
574 unsigned NumRegs = OpInfo.Regs.size();
580 for (Register Reg : OpInfo.Regs) {
604 GISelAsmOperandInfo &OpInfo = OutputOperands[i];
606 if (OpInfo.Regs.empty())
609 switch (OpInfo.ConstraintType) {
612 if (OpInfo.Regs.size() > 1) {
618 Register SrcReg = OpInfo.Regs[0];