Lines Matching defs:MIRBuilder
278 MachineIRBuilder &MIRBuilder) {
292 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
296 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
308 MIRBuilder.buildFNeg(Res, Op1, Flags);
311 return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
314 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
322 MIRBuilder.buildFNeg(Res, Op0, Flags);
327 MachineIRBuilder &MIRBuilder) {
336 MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
338 MIRBuilder.buildCopy(
341 MIRBuilder.buildCopy(
345 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1,
352 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
365 &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
371 return CLI->lowerReturn(MIRBuilder, Ret, VRegs, SwiftErrorVReg);
374 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
382 MIRBuilder.buildBrCond(Tst, TrueBB);
387 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
391 MIRBuilder.buildBr(TgtBB);
826 MachineIRBuilder &MIRBuilder) {
830 MIRBuilder.buildBrIndirect(Tgt);
834 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
855 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
869 Register VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(),
871 MIRBuilder.buildCopy(Regs[0], VReg);
882 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
892 MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
898 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
913 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
915 MIRBuilder.buildCopy(VReg, Vals[0]);
924 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
934 MIRBuilder.buildStore(Vals[i], Addr, *MMO);
964 MachineIRBuilder &MIRBuilder) {
979 MachineIRBuilder &MIRBuilder) {
999 MachineIRBuilder &MIRBuilder) {
1010 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags);
1017 MachineIRBuilder &MIRBuilder) {
1026 MIRBuilder.buildCopy(Regs[0], Src);
1032 MachineIRBuilder &MIRBuilder) {
1036 return translateCopy(U, *U.getOperand(0), MIRBuilder);
1038 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
1042 MachineIRBuilder &MIRBuilder) {
1045 MIRBuilder.buildInstr(Opcode, {Res}, {Op});
1050 MachineIRBuilder &MIRBuilder) {
1068 MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg)
1095 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1096 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0))
1105 IdxReg = MIRBuilder.buildSplatVector(
1109 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
1116 auto ElementSizeMIB = MIRBuilder.buildConstant(
1119 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0);
1123 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
1129 MIRBuilder.buildConstant(OffsetTy, Offset);
1130 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
1134 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
1139 MachineIRBuilder &MIRBuilder,
1147 auto ICall = MIRBuilder.buildIntrinsic(ID, Res, true);
1187 MachineIRBuilder &MIRBuilder) {
1191 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
1208 MachineIRBuilder &MIRBuilder) {
1210 MIRBuilder.buildInstr(
1287 MachineIRBuilder &MIRBuilder) {
1300 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
1328 const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) {
1346 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);
1351 MachineIRBuilder &MIRBuilder) {
1355 if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
1385 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));
1400 MIRBuilder.getDebugLoc()) &&
1411 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
1421 MIRBuilder.getDebugLoc()) &&
1424 MIRBuilder.buildDbgLabel(DI.getLabel());
1437 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)})
1448 MIRBuilder.getDebugLoc()) &&
1453 MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
1455 MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
1462 MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
1468 return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
1470 return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
1472 return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
1474 return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
1476 return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
1478 return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
1480 return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);
1482 return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);
1484 return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
1486 return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
1499 MIRBuilder.buildFMA(Dst, Op0, Op1, Op2,
1503 auto FMul = MIRBuilder.buildFMul(
1505 MIRBuilder.buildFAdd(Dst, FMul, Op2,
1513 return translateMemFunc(CI, MIRBuilder, ID);
1518 MIRBuilder.buildConstant(Reg, TypeID);
1528 getStackGuard(getOrCreateVReg(CI), MIRBuilder);
1533 getStackGuard(GuardVal, MIRBuilder);
1539 MIRBuilder.buildStore(
1558 MIRBuilder.buildCopy(Reg, StackPtr);
1572 MIRBuilder.buildCopy(StackPtr, Reg);
1584 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},
1591 MIRBuilder.buildUndef(Undef);
1604 MIRBuilder
1611 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)
1620 MIRBuilder);
1627 MachineIRBuilder &MIRBuilder) {
1638 MIRBuilder, CB, [&](const Value &Val) { return getOrCreateVRegs(Val); });
1642 MachineIRBuilder &MIRBuilder) {
1653 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
1654 &CB, &MIRBuilder.getMBB(), Arg));
1657 SwiftError.getOrCreateVRegDefAt(&CB, &MIRBuilder.getMBB(), Arg);
1667 CLI->lowerCall(MIRBuilder, CB, Res, Args, SwiftErrorVReg,
1674 HasTailCall = TII->isTailCall(*std::prev(MIRBuilder.getInsertPt()));
1680 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1696 return translateInlineAsm(CI, MIRBuilder);
1706 return translateCallBase(CI, MIRBuilder);
1710 if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1720 MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory());
1766 MachineIRBuilder &MIRBuilder) {
1796 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1798 if (!translateCallBase(I, MIRBuilder))
1802 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1808 MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1809 MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1810 MIRBuilder.buildBr(ReturnMBB);
1816 MachineIRBuilder &MIRBuilder) {
1822 MachineIRBuilder &MIRBuilder) {
1825 MachineBasicBlock &MBB = MIRBuilder.getMBB();
1846 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
1851 MIRBuilder.buildUndef(Undef);
1865 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1873 MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1874 MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1880 MachineIRBuilder &MIRBuilder) {
1889 MIRBuilder.buildFrameIndex(Res, FI);
1903 MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1912 MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1918 auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign.value() - 1);
1919 auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne,
1922 MIRBuilder.buildConstant(IntPtrTy, ~(uint64_t)(StackAlign.value() - 1));
1923 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst);
1928 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment);
1935 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1940 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},
1947 MachineIRBuilder &MIRBuilder) {
1951 return translateCopy(U, *U.getOperand(1), MIRBuilder);
1957 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1962 MachineIRBuilder &MIRBuilder) {
1966 return translateCopy(U, *U.getOperand(0), MIRBuilder);
1984 Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx).getReg(0);
1986 MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1991 MachineIRBuilder &MIRBuilder) {
1998 MIRBuilder
2006 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
2011 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
2020 MachineIRBuilder &MIRBuilder) {
2039 MIRBuilder.buildAtomicCmpXchgWithSuccess(
2049 MachineIRBuilder &MIRBuilder) {
2108 MIRBuilder.buildAtomicRMW(
2118 MachineIRBuilder &MIRBuilder) {
2120 MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
2126 MachineIRBuilder &MIRBuilder) {
2134 MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]);