Lines Matching refs:phases
273 // affect the phase, starting with the earliest phases, and record which
275 phases::ID Driver::getFinalPhase(const DerivedArgList &DAL,
278 phases::ID FinalPhase;
285 FinalPhase = phases::Preprocess;
289 FinalPhase = phases::Precompile;
301 FinalPhase = phases::Compile;
305 FinalPhase = phases::Backend;
309 FinalPhase = phases::Assemble;
313 FinalPhase = phases::Link;
2294 typedef const llvm::SmallVectorImpl<phases::ID> PhasesTy;
2336 phases::ID CurPhase, phases::ID FinalPhase,
2612 phases::ID CurPhase, phases::ID FinalPhase,
2633 if (CompileDeviceOnly || CurPhase == phases::Backend) {
2639 // Skip the phases that were already dealt with.
2649 if (Ph == phases::Assemble)
2696 } else if (CurPhase > phases::Backend) {
2703 assert(CurPhase < phases::Backend && "Generating single CUDA "
2731 phases::ID CurPhase, phases::ID FinalPhase,
2734 // backend and assemble phases to output LLVM IR. Except for generating
2740 assert(((CurPhase == phases::Link && Relocatable) ||
2746 if (!Relocatable && CurPhase == phases::Backend && !EmitLLVM &&
2755 C, Args, phases::Backend, CudaDeviceActions[I],
2758 C, Args, phases::Assemble, BackendAction, AssociatedOffloadKind);
2796 } else if (CurPhase == phases::Link) {
2881 phases::ID CurPhase, phases::ID FinalPhase,
2892 if (CurPhase == phases::Link) {
3097 phases::ID CurPhase, phases::ID FinalPhase,
3325 phases::ID FinalPhase = getFinalPhase(Args, &FinalPhaseArg);
3327 if (FinalPhase == phases::Link) {
3335 if (FinalPhase == phases::Preprocess || Args.hasArg(options::OPT__SLASH_Y_)) {
3355 phases::ID InitialPhase = PL[0];
3374 else if (InitialPhase == phases::Compile &&
3393 if (FinalPhase >= phases::Compile) {
3397 for (phases::ID Phase : types::getCompilationPhases(HeaderType))
3413 if (FinalPhase == phases::Link && LastPLSize == 1) {
3494 for (phases::ID Phase : PL) {
3503 if (Phase == phases::Link) {
3514 if (Phase == phases::IfsMerge) {
3524 if (Phase == phases::Precompile && HeaderModuleAction &&
3586 Args.hasArg(options::OPT_c) ? phases::Compile : phases::LastPhase);
3608 case phases::Compile: {
3618 case phases::IfsMerge: {
3661 Compilation &C, const ArgList &Args, phases::ID Phase, Action *Input,
3668 if (Phase == phases::Assemble && Input->getType() != types::TY_PP_Asm)
3673 case phases::Link:
3675 case phases::IfsMerge:
3677 case phases::Preprocess: {
3697 case phases::Precompile: {
3722 case phases::Compile: {
3742 case phases::Backend: {
3758 case phases::Assemble: