Lines Matching refs:IsSignaling
11836 bool IsSignaling) {
11838 if (IsSignaling)
13674 return getVectorFCmpIR(CmpInst::FCMP_OEQ, /*IsSignaling*/false);
13677 return getVectorFCmpIR(CmpInst::FCMP_OLT, /*IsSignaling*/true);
13680 return getVectorFCmpIR(CmpInst::FCMP_OLE, /*IsSignaling*/true);
13683 return getVectorFCmpIR(CmpInst::FCMP_UNO, /*IsSignaling*/false);
13686 return getVectorFCmpIR(CmpInst::FCMP_UNE, /*IsSignaling*/false);
13689 return getVectorFCmpIR(CmpInst::FCMP_UGE, /*IsSignaling*/true);
13692 return getVectorFCmpIR(CmpInst::FCMP_UGT, /*IsSignaling*/true);
13695 return getVectorFCmpIR(CmpInst::FCMP_ORD, /*IsSignaling*/false);
13720 bool IsSignaling;
13724 case 0x00: Pred = FCmpInst::FCMP_OEQ; IsSignaling = false; break;
13725 case 0x01: Pred = FCmpInst::FCMP_OLT; IsSignaling = true; break;
13726 case 0x02: Pred = FCmpInst::FCMP_OLE; IsSignaling = true; break;
13727 case 0x03: Pred = FCmpInst::FCMP_UNO; IsSignaling = false; break;
13728 case 0x04: Pred = FCmpInst::FCMP_UNE; IsSignaling = false; break;
13729 case 0x05: Pred = FCmpInst::FCMP_UGE; IsSignaling = true; break;
13730 case 0x06: Pred = FCmpInst::FCMP_UGT; IsSignaling = true; break;
13731 case 0x07: Pred = FCmpInst::FCMP_ORD; IsSignaling = false; break;
13732 case 0x08: Pred = FCmpInst::FCMP_UEQ; IsSignaling = false; break;
13733 case 0x09: Pred = FCmpInst::FCMP_ULT; IsSignaling = true; break;
13734 case 0x0a: Pred = FCmpInst::FCMP_ULE; IsSignaling = true; break;
13735 case 0x0b: Pred = FCmpInst::FCMP_FALSE; IsSignaling = false; break;
13736 case 0x0c: Pred = FCmpInst::FCMP_ONE; IsSignaling = false; break;
13737 case 0x0d: Pred = FCmpInst::FCMP_OGE; IsSignaling = true; break;
13738 case 0x0e: Pred = FCmpInst::FCMP_OGT; IsSignaling = true; break;
13739 case 0x0f: Pred = FCmpInst::FCMP_TRUE; IsSignaling = false; break;
13745 IsSignaling = !IsSignaling;
13817 if (IsSignaling)
13824 return getVectorFCmpIR(Pred, IsSignaling);