Lines Matching defs:sc_memr
75 struct resource *sc_memr;
152 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
154 if (sc->sc_memr == NULL) {
174 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f));
175 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
176 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
178 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
181 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
183 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
184 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
185 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
195 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
197 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
198 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
200 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);
204 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
206 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
207 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
208 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
225 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);
229 disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);
231 bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);
232 lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);
234 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
236 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
247 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
254 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
257 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
272 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL);