Lines Matching refs:val
144 uint32_t val;
146 val = ((broadcast_en & 0x1) << 10) |
152 nlm_write_nae_reg(base, XAUI_MAC_FILTER_CFG(nblock), val);
203 uint32_t val;
205 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
206 val &= ~(0x1 << 11); /* clear soft reset */
207 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
209 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
210 val &= ~(0x3 << 11); /* clear soft reset and hard reset */
211 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
216 val = 0x000010A8;
217 val |= XAUI_CONFIG_LENCHK;
218 val |= XAUI_CONFIG_GENFCS;
219 val |= XAUI_CONFIG_PAD_64;
220 nlm_write_nae_reg(nae_base, XAUI_CONFIG1(nblock), val);
227 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock));
228 val |= (0x1 << NETIOR_XGMAC_VLAN_DC_POS);
229 val |= (0x1 << NETIOR_XGMAC_STATS_EN_POS);
231 val |= (0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
232 val |= (0x1 << NETIOR_XGMAC_RX_PFC_EN_POS);
233 val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
235 val &= ~(0x1 << NETIOR_XGMAC_TX_PFC_EN_POS);
236 val |= (0x1 << NETIOR_XGMAC_TX_PAUSE_POS);
238 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL1(nblock), val);
241 val = 0xF1230000; /* PFC mode, offtimer = 0xf123, ontimer = 0 */
243 val = 0x0000F123; /* link level FC mode, offtimer = 0xf123 */
244 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL2(nblock), val);
247 val = nlm_read_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock));
248 val &= ~(0x1f << 10);
249 val |= ~(15 << 10);
250 nlm_write_nae_reg(nae_base, XAUI_NETIOR_XGMAC_CTRL3(nblock), val);