Lines Matching refs:sc_pci_ctrl_base
95 uint32_t sc_pci_ctrl_base; /* XXX until bus stuff is done */
194 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK);
195 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK,
199 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS);
200 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS,
215 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK);
216 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK,
236 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
239 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET, 0);
240 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
242 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET, 4);
243 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
247 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP, 0x1ffc1);
249 (void) ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP);
253 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET);
280 sc->sc_pci_ctrl_base = QCA955X_PCI_CTRL_BASE0;
287 sc->sc_pci_ctrl_base = QCA955X_PCI_CTRL_BASE1;
313 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS, 0);
314 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, 0);
529 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS);
530 mask = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK);