dev/tpm/tpm_tis.c

42 #define	TPM_STS				0x18
283 		burst_count = (RD4(sc, TPM_STS) & TPM_STS_BURST_MASK) >>
388 	OR4(sc, TPM_STS, TPM_STS_CMD_RDY);
389 	bus_barrier(sc->mem_res, TPM_STS, 4, BUS_SPACE_BARRIER_WRITE);
390 	if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_B))
393 	AND4(sc, TPM_STS, ~TPM_STS_CMD_RDY);
424 	if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C)) {
429 	if (RD4(sc, TPM_STS) & TPM_STS_DATA_EXPECTED) {
443 	WR4(sc, TPM_STS, TPM_STS_CMD_START);
444 	bus_barrier(sc->mem_res, TPM_STS, 4, BUS_SPACE_BARRIER_WRITE);
448 	if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, timeout)) {
463 		if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C))