Lines Matching defs:ess
341 agg_codec_wait4idle(struct agg_info *ess)
345 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
355 agg_rdcodec(struct agg_info *ess, int regno)
360 if (agg_codec_wait4idle(ess)) {
362 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
366 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
370 if (!agg_codec_wait4idle(ess)) {
371 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
374 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
382 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
385 if (agg_codec_wait4idle(ess)) {
387 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
391 AGG_WR(ess, PORT_CODEC_REG, data, 2);
392 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
395 if (agg_codec_wait4idle(ess)) {
397 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
405 ringbus_setdest(struct agg_info *ess, int src, int dest)
409 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
412 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
420 wp_rdreg(struct agg_info *ess, u_int16_t reg)
422 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
423 return AGG_RD(ess, PORT_DSP_DATA, 2);
427 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
429 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
430 AGG_WR(ess, PORT_DSP_DATA, data, 2);
434 wp_wait_data(struct agg_info *ess, u_int16_t data)
438 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
442 AGG_WR(ess, PORT_DSP_DATA, data, 2);
449 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
451 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
452 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
453 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
454 return wp_rdreg(ess, WPREG_DATA_PORT);
458 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
460 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
461 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
462 wp_wrreg(ess, WPREG_DATA_PORT, data);
463 if (wp_wait_data(ess, data) != 0)
464 device_printf(ess->dev,
467 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
472 apu_setparam(struct agg_info *ess, int apuch,
475 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
476 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
477 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
478 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
479 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
480 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
481 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
484 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
486 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
490 wp_settimer(struct agg_info *ess, u_int divide)
504 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
505 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
507 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
511 wp_starttimer(struct agg_info *ess)
513 AGG_WR(ess, PORT_INT_STAT, 1, 2);
514 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
515 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
516 wp_wrreg(ess, WPREG_TIMER_START, 1);
520 wp_stoptimer(struct agg_info *ess)
522 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
523 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
524 AGG_WR(ess, PORT_INT_STAT, 1, 2);
525 wp_wrreg(ess, WPREG_TIMER_START, 0);
534 wc_rdreg(struct agg_info *ess, u_int16_t reg)
536 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
537 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
542 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
544 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
545 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
550 wc_rdchctl(struct agg_info *ess, int ch)
552 return wc_rdreg(ess, ch << 3);
557 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
559 wc_wrreg(ess, ch << 3, data);
566 agg_stopclock(struct agg_info *ess, int part, int st)
570 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
580 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
590 agg_initcodec(struct agg_info* ess)
594 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
595 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
599 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
601 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
604 if (agg_rdcodec(ess, 0) < 0) {
605 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
609 device_printf(ess->dev, "will perform cold reset.\n");
610 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
611 if (pci_read_config(ess->dev, 0x58, 2) & 1)
613 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
614 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
615 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
616 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
618 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
620 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
621 agg_sleep(ess, "agginicd", 500);
622 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
624 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
630 agg_init(struct agg_info* ess)
637 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
639 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
645 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
649 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
654 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
656 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
658 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
660 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
663 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
664 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
665 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
666 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
667 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
668 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
669 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
672 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
675 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
676 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
677 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
678 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
681 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
683 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
685 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
687 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
692 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
697 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
699 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
701 AGG_WR(ess, PORT_WAVCACHE_CTRL,
705 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
708 agg_initcodec(ess);
709 AGG_WR(ess, PORT_RINGBUS_CTRL,
712 wp_wrreg(ess, 0x08, 0xB004);
713 wp_wrreg(ess, 0x09, 0x001B);
714 wp_wrreg(ess, 0x0A, 0x8000);
715 wp_wrreg(ess, 0x0B, 0x3F37);
716 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
717 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
718 ringbus_setdest(ess, RINGBUS_SRC_ADC,
720 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
724 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
726 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
727 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
730 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
731 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
732 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
738 switch (pci_get_subvendor(ess->dev)
739 | (pci_get_subdevice(ess->dev) << 16)) {
744 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
745 AGG_WR(ess, PORT_GPIO_DIR,
746 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
747 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
754 agg_power(struct agg_info *ess, int status)
758 lastpwr = ess->curpwr;
767 pci_set_powerstate(ess->dev, status);
769 agg_wrcodec(ess, AC97_REG_POWER, 0);
772 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
773 device_printf(ess->dev,
776 AGG_WR(ess, PORT_RINGBUS_CTRL,
777 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
781 AGG_WR(ess, PORT_RINGBUS_CTRL,
782 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
787 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
789 agg_init(ess);
793 pci_set_powerstate(ess->dev, status);
801 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
803 agg_init(ess);
808 AGG_WR(ess, PORT_RINGBUS_CTRL,
809 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
812 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
816 pci_set_powerstate(ess->dev, status);
820 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
822 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
825 wp_stoptimer(ess);
826 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
827 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
828 pci_set_powerstate(ess->dev, status);
836 ess->curpwr = status;
1213 set_timer(struct agg_info *ess)
1218 for (i = 0; i < ess->playchns; i++)
1219 if ((ess->active & (1 << i)) &&
1220 (dv > (newdv = calc_timer_div(ess->pch + i))))
1222 if ((ess->active & (1 << i)) &&
1223 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1226 wp_settimer(ess, dv);
1239 struct agg_info *ess = sc;
1241 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1247 struct agg_info *ess = sc;
1250 /* XXX sound locking violation: agg_lock(ess); */
1251 ret = agg_rdcodec(ess, regno);
1252 /* agg_unlock(ess); */
1259 struct agg_info *ess = sc;
1262 /* XXX sound locking violation: agg_lock(ess); */
1263 ret = agg_wrcodec(ess, regno, data);
1264 /* agg_unlock(ess); */
1286 struct agg_info *ess = devinfo;
1293 ch = ess->pch + ess->playchns;
1295 ch->parent = ess;
1298 ch->num = ess->playchns;
1300 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr, &ch->map);
1306 sndbuf_setup(b, p, ess->bufsz);
1309 ess->playchns++;
1360 struct agg_info *ess = ch->parent;
1363 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer), ch->map);
1495 struct agg_info *ess = devinfo;
1501 ch = &ess->rch;
1503 ch->parent = ess;
1508 p = ess->stat + ess->bufsz;
1509 ch->phys = ess->phys + ess->bufsz;
1510 ch->base = ess->phys;
1511 ch->src = (int16_t *)(p + ess->bufsz);
1512 ch->srcphys = ch->phys + ess->bufsz;
1515 sndbuf_setup(b, p, ess->bufsz);
1634 struct agg_info* ess = sc;
1639 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1644 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1648 agg_lock(ess);
1650 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1651 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1653 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1654 if (ess->active & m)
1655 suppress_jitter(ess->pch + i);
1657 if (ess->active & m)
1658 suppress_rec_jitter(&ess->rch);
1659 agg_unlock(ess);
1661 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1662 if (ess->active & m) {
1663 if (ess->curpwr <= PCI_POWERSTATE_D1)
1664 chn_intr(ess->pch[i].channel);
1671 if ((ess->active & m)
1672 && ess->curpwr <= PCI_POWERSTATE_D1)
1673 chn_intr(ess->rch.channel);
1677 agg_unlock(ess);
1684 agg_lock(ess);
1685 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1686 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1687 agg_unlock(ess);
1691 mixer_hwvol_step(ess->dev, 1, 1);
1694 mixer_hwvol_step(ess->dev, -1, -1);
1700 mixer_hwvol_mute(ess->dev);
1703 device_printf(ess->dev,
1705 device_get_nameunit(ess->dev), event);
1776 struct agg_info *ess = NULL;
1787 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1788 ess->dev = dev;
1790 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1792 if (!mtx_initialized(&ess->lock)) {
1807 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1812 /*size */ ess->bufsz, 1, 0x3ffff,
1815 &ess->buf_dmat) != 0) {
1826 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1829 &ess->stat_dmat) != 0) {
1836 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys,
1837 &ess->stat_map);
1838 if (ess->stat == NULL) {
1845 (long long)ess->phys);
1848 ess->curpwr = PCI_POWERSTATE_D3;
1856 ess->reg = reg;
1857 ess->regid = regid;
1858 ess->st = rman_get_bustag(reg);
1859 ess->sh = rman_get_bushandle(reg);
1868 ess->irq = irq;
1869 ess->irqid = irqid;
1877 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1882 ess->ih = ih;
1885 agg_lock(ess);
1886 agg_power(ess, PCI_POWERSTATE_D0);
1887 if (agg_rdcodec(ess, 0) == 0x80) {
1889 agg_unlock(ess);
1894 agg_unlock(ess);
1895 codec = AC97_CREATE(dev, ess, agg_ac97);
1906 ess->codec = codec;
1908 ret = pcm_register(dev, ess, dacn, 1);
1913 agg_lock(ess);
1914 agg_power(ess, powerstate_init);
1915 agg_unlock(ess);
1917 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1918 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1919 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1938 if (ess != NULL) {
1939 if (ess->stat != NULL)
1940 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1941 if (ess->stat_dmat != NULL)
1942 bus_dma_tag_destroy(ess->stat_dmat);
1943 if (ess->buf_dmat != NULL)
1944 bus_dma_tag_destroy(ess->buf_dmat);
1945 if (mtx_initialized(&ess->lock))
1946 mtx_destroy(&ess->lock);
1947 free(ess, M_DEVBUF);
1956 struct agg_info *ess = pcm_getdevinfo(dev);
1960 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1961 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1963 agg_lock(ess);
1964 if (ess->active) {
1965 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1966 agg_unlock(ess);
1969 agg_unlock(ess);
1973 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1977 agg_lock(ess);
1978 agg_power(ess, PCI_POWERSTATE_D3);
1979 agg_unlock(ess);
1981 bus_teardown_intr(dev, ess->irq, ess->ih);
1982 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1983 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1984 dma_free(ess->stat_dmat, ess->stat, ess->stat_map);
1985 bus_dma_tag_destroy(ess->stat_dmat);
1986 bus_dma_tag_destroy(ess->buf_dmat);
1987 mtx_destroy(&ess->lock);
1988 free(ess, M_DEVBUF);
1995 struct agg_info *ess = pcm_getdevinfo(dev);
1997 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1998 agg_lock(ess);
1999 agg_power(ess, PCI_POWERSTATE_D3);
2000 agg_unlock(ess);
2009 struct agg_info *ess = pcm_getdevinfo(dev);
2011 for (i = 0; i < ess->playchns; i++)
2012 if (ess->active & (1 << i))
2013 aggch_start_dac(ess->pch + i);
2014 if (ess->active & (1 << i))
2015 aggch_start_adc(&ess->rch);
2017 agg_lock(ess);
2018 if (!ess->active)
2019 agg_power(ess, powerstate_init);
2020 agg_unlock(ess);
2033 struct agg_info *ess = pcm_getdevinfo(dev);
2035 agg_lock(ess);
2036 agg_power(ess, PCI_POWERSTATE_D3);
2037 agg_unlock(ess);