Lines Matching refs:WRITE_OFFSET32
233 WRITE_OFFSET32(ha, Q8_CRB_WINDOW_2M, offset);
248 WRITE_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000), *val);
266 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_ADDR_LO, (uint32_t)addr);
267 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_ADDR_HI, (uint32_t)(addr >> 32));
270 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_LO, val->data_lo);
271 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_HI, val->data_hi);
272 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_ULO, val->data_ulo);
273 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_UHI, val->data_uhi);
274 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_CTRL, 0x07); /* Write */
276 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_CTRL, 0x03); /* Read */
315 WRITE_OFFSET32(ha, Q8_ROM_LOCKID, 0xa5a5a5a5);
356 WRITE_OFFSET32(ha, Q8_ROM_LOCKID, 0xa5a5a5a5);
477 WRITE_OFFSET32(ha, Q8_PEG_D_RESET1, 0x001E);
478 WRITE_OFFSET32(ha, Q8_PEG_D_RESET2, 0x0008);
479 WRITE_OFFSET32(ha, Q8_PEG_I_RESET, 0x0008);
480 WRITE_OFFSET32(ha, Q8_PEG_0_CLR1, 0x0000);
481 WRITE_OFFSET32(ha, Q8_PEG_0_CLR2, 0x0000);
482 WRITE_OFFSET32(ha, Q8_PEG_1_CLR1, 0x0000);
483 WRITE_OFFSET32(ha, Q8_PEG_1_CLR2, 0x0000);
484 WRITE_OFFSET32(ha, Q8_PEG_2_CLR1, 0x0000);
485 WRITE_OFFSET32(ha, Q8_PEG_2_CLR2, 0x0000);
486 WRITE_OFFSET32(ha, Q8_PEG_3_CLR1, 0x0000);
487 WRITE_OFFSET32(ha, Q8_PEG_3_CLR2, 0x0000);
488 WRITE_OFFSET32(ha, Q8_PEG_4_CLR1, 0x0000);
489 WRITE_OFFSET32(ha, Q8_PEG_4_CLR2, 0x0000);
557 WRITE_OFFSET32(ha, Q8_CMDPEG_STATE, 0x00000000);
558 WRITE_OFFSET32(ha, Q8_PEG_0_RESET, 0x00001020);
559 WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0x0080001E);