Lines Matching refs:val
206 qla_rdwr_indreg32(qla_host_t *ha, uint32_t addr, uint32_t *val, uint32_t rd)
246 *val = READ_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000));
248 WRITE_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000), *val);
260 qla_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr, offchip_mem_val_t *val,
270 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_LO, val->data_lo);
271 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_HI, val->data_hi);
272 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_ULO, val->data_ulo);
273 WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_UHI, val->data_uhi);
283 val->data_lo = READ_OFFSET32(ha, \
285 val->data_hi = READ_OFFSET32(ha, \
287 val->data_ulo = READ_OFFSET32(ha, \
289 val->data_uhi = READ_OFFSET32(ha, \
308 uint32_t val;
317 val = addr;
318 qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);
319 val = 0;
320 qla_rdwr_indreg32(ha, Q8_ROM_DUMMY_BYTE_COUNT, &val, 0);
321 val = 3;
322 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
326 val = ROM_OPCODE_FAST_RD;
327 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
329 while (!((val = READ_OFFSET32(ha, Q8_ROM_STATUS)) & BIT_1)) {
337 val = 0;
338 qla_rdwr_indreg32(ha, Q8_ROM_DUMMY_BYTE_COUNT, &val, 0);
339 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
418 uint32_t val = 0, sig = 0;
423 QL_DPRINT2((ha->pci_dev, "%s: val[0] = 0x%08x\n", __func__, sig));
425 qla_rd_flash32(ha, 4, &val);
426 QL_DPRINT2((ha->pci_dev, "%s: val[4] = 0x%08x\n", __func__, val));
428 count = val >> 16;
429 offset = val & 0xFFFF;
432 QL_DPRINT2((ha->pci_dev, "%s: [sig,val]=[0x%08x, 0x%08x] %d pairs\n",
433 __func__, sig, val, count));
502 offchip_mem_val_t val;
507 qla_rd_flash32(ha, flash_off, &val.data_lo);
511 qla_rd_flash32(ha, flash_off, &val.data_hi);
515 qla_rd_flash32(ha, flash_off, &val.data_ulo);
519 qla_rd_flash32(ha, flash_off, &val.data_uhi);
523 qla_rdwr_offchip_mem(ha, mem_off, &val, 0);
598 uint32_t val, delay = 300;
608 val = READ_OFFSET32(ha, Q8_CMDPEG_STATE);
610 if (val == CMDPEG_PHAN_INIT_COMPLETE) {
622 val = READ_OFFSET32(ha, Q8_CMDPEG_STATE);
624 if (val != CMDPEG_PHAN_INIT_COMPLETE) {
632 if (qla_rd_flash32(ha, 0x100004, &val) == 0) {
634 if (((val & 0xFF) != ha->fw_ver_major) ||
635 (((val >> 8) & 0xFF) != ha->fw_ver_minor) ||
636 (((val >> 16) & 0xFF) != ha->fw_ver_sub)) {
657 uint32_t val;
662 val = READ_OFFSET32(ha, Q8_ROM_STATUS);
664 if (val & BIT_1)
674 uint32_t val, rval;
676 val = 0;
677 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
679 val = ROM_OPCODE_WR_ENABLE;
680 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
693 uint32_t val, rval;
698 val = 0;
699 qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
701 val = ROM_OPCODE_WR_STATUS_REG;
702 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
714 val = 0;
715 qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
717 val = ROM_OPCODE_WR_STATUS_REG;
718 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
731 uint32_t val, rval;
736 val = 0x9C;
737 qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
739 val = ROM_OPCODE_WR_STATUS_REG;
740 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
754 uint32_t val, rval;
757 val = 0;
758 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
760 val = ROM_OPCODE_RD_STATUS_REG;
761 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
766 qla_rdwr_indreg32(ha, Q8_ROM_RD_DATA, &val, 1);
768 if ((val & BIT_0) == 0)
769 return (val);
811 uint32_t val;
817 val = start;
818 qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);
820 val = 3;
821 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
823 val = ROM_OPCODE_SECTOR_ERASE;
824 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
871 uint32_t val;
874 val = data;
875 qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);
877 val = off;
878 qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);
880 val = 3;
881 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
883 val = ROM_OPCODE_PROG_PAGE;
884 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
897 uint32_t val, count = 1000;
902 val = 0;
903 qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
905 val = ROM_OPCODE_RD_STATUS_REG;
906 qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
912 qla_rdwr_indreg32(ha, Q8_ROM_RD_DATA, &val, 1);
914 if ((val & BIT_0) == 0)