Lines Matching refs:IGU_REG_COMMAND_REG_CTRL
41831 #define IGU_REG_COMMAND_REG_CTRL 0x180848UL //Access:W DataWidth:0x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.