Lines Matching refs:physAddrUpper
4157 TI_DBG2(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment));
4183 agMemoryRequirement.agMemory[i].phyAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper;
4206 loResource->loLevelMem.mem[i].physAddrUpper,
4409 dmMemRequirement.dmMemory[i-LLMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper;
4419 loResource->loLevelMem.mem[i].physAddrUpper,
4454 smMemRequirement.smMemory[i-LLMemCount-DMMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper;
4464 loResource->loLevelMem.mem[i].physAddrUpper,
4499 dmMemRequirement.dmMemory[i-LLMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper;
4507 TI_DBG6(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment));
4535 smMemRequirement.smMemory[i-LLMemCount].physAddrUpper = loResource->loLevelMem.mem[i].physAddrUpper;
4543 TI_DBG6(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment));