Lines Matching refs:physAddrLower
4157 TI_DBG2(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment));
4184 agMemoryRequirement.agMemory[i].phyAddrLower = loResource->loLevelMem.mem[i].physAddrLower;
4207 loResource->loLevelMem.mem[i].physAddrLower,
4410 dmMemRequirement.dmMemory[i-LLMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower;
4420 loResource->loLevelMem.mem[i].physAddrLower,
4455 smMemRequirement.smMemory[i-LLMemCount-DMMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower;
4465 loResource->loLevelMem.mem[i].physAddrLower,
4500 dmMemRequirement.dmMemory[i-LLMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower;
4507 TI_DBG6(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment));
4536 smMemRequirement.smMemory[i-LLMemCount].physAddrLower = loResource->loLevelMem.mem[i].physAddrLower;
4543 TI_DBG6(("tiCOMPortInit: index %d phyAddrUpper 0x%x phyAddrLower 0x%x totalLength %d alignment %d\n", i, loResource->loLevelMem.mem[i].physAddrUpper, loResource->loLevelMem.mem[i].physAddrLower, loResource->loLevelMem.mem[i].totalLength, loResource->loLevelMem.mem[i].alignment));