Lines Matching refs:SA_DBG1
97 SA_DBG1(("saGetRequirements:agRoot %p swConfig %p memoryRequirement %p usecsPerTick %p maxNumLocks %p\n",agRoot, swConfig,memoryRequirement,usecsPerTick,maxNumLocks));
98 SA_DBG1(("saGetRequirements: usecsPerTick 0x%x (%d)\n",*usecsPerTick,*usecsPerTick));
113 SA_DBG1(("saGetRequirements: agMemory[LLROOT_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
127 SA_DBG1(("saGetRequirements: agMemory[DEVICELINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
145 SA_DBG1(("saGetRequirements: agMemory[IOREQLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
158 SA_DBG1(("saGetRequirements: agMemory[TIMERLINK_MEM_INDEX] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
174 SA_DBG1(("saGetRequirements: agMemory[LL_FUNCTION_TRACE] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
195 SA_DBG1(("saGetRequirements: agMemory[LL_FAST_IO] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
216 SA_DBG1(("saGetRequirements: agMemory[HDA_DMA_BUFFER] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
232 SA_DBG1(("saGetRequirements:MPI agMemory[%d] singleElementLength = 0x%x totalLength = 0x%x align = 0x%x type %x\n",
246 SA_DBG1(("saGetRequirements: param3 == agNULL maxNumLocks %d\n", *maxNumLocks ));
253 SA_DBG1(("saGetRequirements: maxNumLocks %d\n", *maxNumLocks ));
269 SA_DBG1(("saGetRequirements: swConfig->stallUsec %d\n",swConfig->stallUsec ));
272 SA_DBG1(("saGetRequirements: swConfig->disableMDF %d\n",swConfig->disableMDF));
274 /*SA_DBG1(("saGetRequirements: swConfig->enableDIF %d\n",swConfig->enableDIF ));*/
275 /*SA_DBG1(("saGetRequirements: swConfig->enableEncryption %d\n",swConfig->enableEncryption ));*/
345 SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n", WAIT_INCREMENT ));
346 SA_DBG1(("saInitialize: usecsPerTick %d\n", usecsPerTick ));
351 SA_DBG1(("saInitialize: ossaHwRegReadConfig32 ID reads as %08X\n", ossaHwRegReadConfig32(agRoot,0 ) ));
352 SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCV, VEN_DEV_SPCVE));
353 SA_DBG1(("saInitialize: expect %08X or %08X or\n", VEN_DEV_SPCVP, VEN_DEV_SPCVEP));
354 SA_DBG1(("saInitialize: expect %08X or %08X\n", VEN_DEV_ADAPVEP, VEN_DEV_ADAPVP));
361 SA_DBG1(("saInitialize: Macro error !smIS_SPC %d smIS_SPCv %d smIS_SFC %d\n",smIS_SPC(agRoot),smIS_SPCV(agRoot), smIS_SFC(agRoot) ));
376 SA_DBG1(("saInitialize:AGSA_RC_FAILURE Memory[%d] singleElementLength = 0x%x numElements = 0x%x NOT allocated\n",
385 SA_DBG1(("saInitialize: Memory[%d] singleElementLength = 0x%x numElements = 0x%x allocated %p\n",
399 SA_DBG1(("saInitialize:AGSA_RC_FAILURE saRoot\n"));
405 SA_DBG1(("saInitialize: saRoot %p\n",saRoot));
428 SA_DBG1(("saInitialize: gLLDebugLevel %x\n",gLLDebugLevel));
472 SA_DBG1(("saInitialize: swConfig->PortRecoveryResetTimer %x\n",swConfig->PortRecoveryResetTimer ));
474 SA_DBG1(("saInitialize: hwDEVICE_ID_VENDID 0x%08x\n", ossaHwRegReadConfig32(agRoot,0)));
475 SA_DBG1(("saInitialize: CFGSTAT CFGCMD 0x%08x\n", ossaHwRegReadConfig32(agRoot,4)));
476 SA_DBG1(("saInitialize: CLSCODE REVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,8)));
477 SA_DBG1(("saInitialize: BIST DT HDRTYPE LATTIM CLSIZE 0x%08x\n", ossaHwRegReadConfig32(agRoot,12)));
478 SA_DBG1(("saInitialize: hwSVID 0x%08x\n", ossaHwRegReadConfig32(agRoot,44)));
483 SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER a 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger));
487 SA_DBG1(("saInitialize: SA_ENABLE_PCI_TRIGGER 0x%08x %p\n", saRoot->swConfig.PCI_trigger,&saRoot->swConfig.PCI_trigger));
496 SA_DBG1(("saInitialize: saRoot->ChipId 0x%08x\n", saRoot->ChipId));
503 SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" ));
508 SA_DBG1(("saInitialize: SPC \n" ));
512 SA_DBG1(("saInitialize: SPC HIL\n" ));
515 SA_DBG1(("saInitialize: smIS_SPC macro fail !!!!\n" ));
522 SA_DBG1(("saInitialize: SPC V\n" ));
525 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
532 SA_DBG1(("saInitialize: SPC VE\n" ));
535 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
542 SA_DBG1(("saInitialize: SPC VP\n" ));
545 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
552 SA_DBG1(("saInitialize: SPC VEP\n" ));
555 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
562 SA_DBG1(("saInitialize: Adaptec 8088\n" ));
566 SA_DBG1(("saInitialize: Adaptec 8089\n" ));
570 SA_DBG1(("saInitialize: SPC 12V\n" ));
573 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
580 SA_DBG1(("saInitialize: SPC 12VE\n" ));
583 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
590 SA_DBG1(("saInitialize: SPC 12VP\n" ));
593 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
600 SA_DBG1(("saInitialize: SPC 12VEP\n" ));
603 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
610 SA_DBG1(("saInitialize: SPC 12ADP\n" ));
613 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
620 SA_DBG1(("saInitialize: SPC 12ADPE\n" ));
623 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
630 SA_DBG1(("saInitialize: SPC 12ADPP\n" ));
633 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
640 SA_DBG1(("saInitialize: SPC 12ADPEP\n" ));
643 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
650 SA_DBG1(("saInitialize: SPC12SATA\n" ));
653 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
660 SA_DBG1(("saInitialize: SPC 12V FPGA\n" ));
663 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
670 SA_DBG1(("saInitialize: SPC 12V FPGA B\n" ));
673 SA_DBG1(("saInitialize: smIS_SPCV macro fail !!!!\n" ));
680 SA_DBG1(("saInitialize: SFC \n" ));
684 SA_DBG1(("saInitialize saRoot->ChipId %8X expect %8X or %8X\n", saRoot->ChipId,VEN_DEV_SPC, VEN_DEV_SPCV));
692 SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgSpcREV_A(agRoot),smIsCfgSpcREV_B(agRoot),smIsCfgSpcREV_C(agRoot)));
696 SA_DBG1(("saInitialize: Rev is A %d B %d C %d\n",smIsCfgVREV_A(agRoot),smIsCfgVREV_B(agRoot),smIsCfgVREV_C(agRoot)));
701 SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,128),
707 SA_DBG1(("saInitialize: LINK_CTRL 0x%08x Speed 0x%X Lanes 0x%X \n", ossaHwRegReadConfig32(agRoot,208),
712 SA_DBG1(("saInitialize: V_SoftResetRegister %08X\n", ossaHwRegReadExt(agRoot, PCIBAR0, V_SoftResetRegister )));
715 SA_DBG1(("saInitialize:TOP_BOOT_STRAP STRAP_BIT %X\n", ossaHwRegReadExt(agRoot, PCIBAR1, 0) ));
717 SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_DEVICE_ID), SPC_TOP_DEVICE_ID));
718 SA_DBG1(("SPC_REG_TOP_DEVICE_ID %8X expect %08X\n", siHalRegReadExt( agRoot, GEN_SPC_REG_TOP_DEVICE_ID,SPC_REG_TOP_DEVICE_ID ) , SPC_TOP_DEVICE_ID));
720 SA_DBG1(("SPC_REG_TOP_BOOT_STRAP %8X expect %08X\n", ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_TOP_BOOT_STRAP), SPC_TOP_BOOT_STRAP));
722 SA_DBG1(("swConfig->numSASDevHandles =%d\n", swConfig->numDevHandles));
752 SA_DBG1(("saInitialize: swConfig->PCI_trigger= 0x%x\n", swConfig->PCI_trigger));
908 SA_DBG1(("saInitialize: WAIT_INCREMENT %d\n" ,WAIT_INCREMENT ));
980 SA_DBG1(("saInitialize:InterruptCoalescingTimer should not be zero. Force to 1\n"));
987 SA_DBG1(("saInitialize failure queue number=%d\n", saRoot->QueueConfig.numInboundQueues));
1019 SA_DBG1(("saInitialize: Zero memory region %d virt %p allocated %d\n",
1030 SA_DBG1(("saInitialize: configured as polling mode\n"));
1035 SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %d\n",swConfig->max_MSI_InterruptVectors));
1036 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %d\n",swConfig->max_MSIX_InterruptVectors));
1043 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors A\n"));
1051 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors B\n"));
1059 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors C\n"));
1067 SA_DBG1(("saInitialize:AGSA_RC_FAILURE InterruptVectors D\n"));
1076 SA_DBG1(("saInitialize: SPC interrupts\n" ));
1106 SA_DBG1(("saInitialize: SPC V interrupts\n" ));
1109 SA_DBG1(("saInitialize: SPC V legacyInt_X\n" ));
1116 SA_DBG1(("saInitialize: SPC V max_MSIX_InterruptVectors %X\n", swConfig->max_MSIX_InterruptVectors));
1123 SA_DBG1(("saInitialize: SPC V max_MSI_InterruptVectors\n" ));
1131 SA_DBG1(("saInitialize: SPC V polling mode\n" ));
1136 SA_DBG1(("saInitialize: SPC V\n" ));
1142 SA_DBG1(("saInitialize: Use 64 bits for interrupts %d %d\n" ,saRoot->Use64bit, saRoot->QueueConfig.numOutboundQueues ));
1146 SA_DBG1(("saInitialize: Use 32 bits for interrupts %d %d\n",saRoot->Use64bit , saRoot->QueueConfig.numOutboundQueues ));
1150 SA_DBG1(("saInitialize: Inbound locking defined since LL_IOREQ_IBQ0_LOCK %d\n",LL_IOREQ_IBQ0_LOCK));
1155 SA_DBG1(("saInitialize: DisableInterrupts sysIntsActive %X\n" ,saRoot->sysIntsActive));
1175 SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0)));
1176 SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)));
1177 SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2)));
1178 SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3)));
1193 SA_DBG1(("saInitialize:Warning Encryption Issue SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3)));
1208 SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode\n"));
1215 SA_DBG1(("saInitialize:1 Going to HDA mode HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET)));
1219 SA_DBG1(("saInitialize: Double_Reset_HDA HDA 0x%X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET)));
1231 SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n"));
1239 SA_DBG1(("saInitialize: 2 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET)));
1244 SA_DBG1(("saInitialize: could not start HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET)));
1258 SA_DBG1(("saInitialize: No HDA mode enable and FW is not running.\n"));
1266 SA_DBG1(("saInitialize: SPCv swConfig->hostDirectAccessMode %d swConfig->hostDirectAccessSupport %d\n",swConfig->hostDirectAccessMode,swConfig->hostDirectAccessSupport));
1272 SA_DBG1(("saInitialize: SPCv load HDA\n"));
1276 SA_DBG1(("saInitialize: hda_status 0x%x\n",hda_status));
1286 SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status\n"));
1295 SA_DBG1(("saInitialize: hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status));
1300 SA_DBG1(("saInitialize: 2 reset hda_status not SPC_V_HDAR_IDLE 0x%08x\n", hda_status));
1306 SA_DBG1(("saInitialize:AGSA_RC_FAILURE soft_reset_status A\n"));
1314 SA_DBG1(("saInitialize:AGSA_RC_FAILURE siHDAMode_V\n"));
1326 SA_DBG1(("saInitialize: SPCv normal\n"));
1347 SA_DBG1(("saInitialize: siBar4Shift FAILED ******************************************\n"));
1354 SA_DBG1(("saInitialize: saRoot->ChipId == VEN_DEV_SPCV\n"));
1360 SA_DBG1(("saInitialize: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", saRoot->ControllerInfo.maxPendingIO,saRoot->swConfig.maxActiveIOs ));
1369 SA_DBG1(("saInitialize: 3 Going to HDA mode HDA %X \n",ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET)));
1377 SA_DBG1(("saInitialize: AGSA_RC_FAILURE mpiInitialize\n"));
1378 SA_DBG1(("saInitialize: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_0_Register)));
1379 SA_DBG1(("saInitialize: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_1_Register)));
1380 SA_DBG1(("saInitialize: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_2_Register)));
1381 SA_DBG1(("saInitialize: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegRead(agRoot, V_Scratchpad_3_Register)));
1396 SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingTimer\n" ));
1397 SA_DBG1(("saInitialize: SPC_V Not set hwInterruptCoalescingControl\n" ));
1406 SA_DBG1(("saInitialize: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable));
1408 SA_DBG1(("saInitialize: saRoot->swConfig.fatalErrorInterruptVector %X\n",saRoot->swConfig.fatalErrorInterruptVector));
1409 SA_DBG1(("saInitialize: swConfig->max_MSI_InterruptVectors %X\n",swConfig->max_MSI_InterruptVectors));
1410 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors));
1411 SA_DBG1(("saInitialize: swConfig->legacyInt_X %X\n",swConfig->legacyInt_X));
1412 SA_DBG1(("saInitialize: swConfig->hostDirectAccessSupport %X\n",swConfig->hostDirectAccessSupport));
1413 SA_DBG1(("saInitialize: swConfig->hostDirectAccessMode %X\n",swConfig->hostDirectAccessMode));
1416 SA_DBG1(("saInitialize: swConfig->disableMDF %X\n",swConfig->disableMDF));
1418 /*SA_DBG1(("saInitialize: swConfig->enableDIF %X\n",swConfig->enableDIF));*/
1419 /*SA_DBG1(("saInitialize: swConfig->enableEncryption %X\n",swConfig->enableEncryption));*/
1425 SA_DBG1(("saInitialize:AGSA_RC_FAILURE mpiInitialize\n"));
1444 SA_DBG1(("saInitialize: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive));
1448 SA_DBG1(("saInitialize: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx));
1453 SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptEnable %d\n",saRoot->swConfig.fatalErrorInterruptEnable));
1454 SA_DBG1(("saInitialize: swConfig.fatalErrorInterruptVector %d\n",saRoot->swConfig.fatalErrorInterruptVector));
1455 SA_DBG1(("saInitialize: swConfig->max_MSIX_InterruptVectors %X\n",swConfig->max_MSIX_InterruptVectors));
1460 SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n",
1463 SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n",
1469 SA_DBG1(("saInitialize: Doorbell_Set %08X U %08X\n",
1472 SA_DBG1(("saInitialize: Doorbell_Mask %08X U %08X\n",
1478 SA_DBG1(("saInitialize: siDumpActiveIORequests\n"));
1508 SA_DBG1(("siReadControllerStatus: Msgu %d Iop %d\n",saRoot->mpiGSTable.MsguTcnt, saRoot->mpiGSTable.IopTcnt));
1527 SA_DBG1(("siReadControllerStatus: saRoot->sysIntsActive %X\n",saRoot->sysIntsActive));
1528 SA_DBG1(("siReadControllerStatus: PI 0x%03x CI 0x%03x\n",circularQ->producerIdx, circularQ->consumerIdx));
1530 SA_DBG1(("siReadControllerStatus:IN MSGU_READ_ODMR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODMR, V_Outbound_Doorbell_Mask_Set_Register )));
1531 SA_DBG1(("siReadControllerStatus:MSGU_READ_ODR %08X\n",siHalRegReadExt(agRoot, GEN_MSGU_ODR, V_Outbound_Doorbell_Set_Register)));
1574 SA_DBG1(("siConfiguration: si_memset mpiConfig\n"));
1581 SA_DBG1(("siConfiguration:custset %8X %8X\n",mpiConfig->mainConfig.custset,swConfig->FWConfig));
1585 SA_DBG1(("siConfiguration: swConfig->param3 == agNULL\n"));
1644 SA_DBG1(("siConfiguration: swConfig->param3 == %p\n",queueConfig));
1650 SA_DBG1(("siConfiguration:AGSA_RC_FAILURE MAX_Q\n"));
1659 SA_DBG1(("siConfiguration:AGSA_RC_FAILURE NO_Q\n"));
1718 SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptEnable %X\n",swConfig->fatalErrorInterruptEnable));
1719 SA_DBG1(("siConfiguration: swConfig->fatalErrorInterruptVector %X\n",swConfig->fatalErrorInterruptVector));
1799 SA_DBG1(("siConfiguration:mpiConfig->mainConfig.FatalErrorInterrupt 0x%X\n",mpiConfig->mainConfig.FatalErrorInterrupt));
1800 SA_DBG1(("siConfiguration:swConfig->fatalErrorInterruptVector 0x%X\n",swConfig->fatalErrorInterruptVector));
1801 SA_DBG1(("siConfiguration:enable64 0x%X\n",enable64));
1802 SA_DBG1(("siConfiguration:PortRecoveryResetTimer 0x%X\n",swConfig->PortRecoveryResetTimer));
1873 SA_DBG1(("mpiInitialize: Entering\n"));
1888 SA_DBG1(("mpiInitialize: saRoot == agNULL\n"));
1900 SA_DBG1(("mpiInitialize: siBar4Shift FAILED ******************************************\n"));
1911 SA_DBG1(("mpiInitialize: mpiWaitForConfigTable FAILED ******************************************\n"));
1923 SA_DBG1(("mpiInitialize: MSGUCfgTblBase = 0x%x\n", MSGUCfgTblBase));
1928 SA_DBG1(("mpiInitialize: Number of PHYs = 0x%x\n", phycount));
1937 SA_DBG1(("mpiInitialize: High Priority IQ support from SPC\n"));
1942 SA_DBG1(("mpiInitialize: Interrupt Coalescing support from SPC\n"));
1959 SA_DBG1(("mpiInitialize: Number of IQ %d\n", maxinbound));
1960 SA_DBG1(("mpiInitialize: Number of OQ %d\n", maxoutbound));
1983 SA_DBG1(("ERROR: The memory region [%d] 0x%X != 0x%X does not have the size of the MSGU event log ******************************************\n",
2004 SA_DBG1(("mpiInitialize:custset V %8X\n",mainCfg.custset));
2005 SA_DBG1(("mpiInitialize:portRecoveryResetTimer V %8X\n",mainCfg.portRecoveryResetTimer));
2008 SA_DBG1(("mpiInitialize:interruptReassertionDelay V %8X\n", mainCfg.interruptReassertionDelay));
2025 SA_DBG1(("mpiInitialize:custset spc %8X\n",mainCfg.custset));
2041 SA_DBG1(("ERROR: The memory region does not have the size of the IOP event log\n"));
2052 SA_DBG1(("mpiInitialize: iQNPPD_HPPD_GEvent 0x%x\n", mainCfg.iQNPPD_HPPD_GEvent));
2154 SA_DBG1(("mpiInitialize:SPCV - MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE\n" ));
2158 SA_DBG1(("mpiInitialize:SPCV - END_TO_END_CRC On\n" ));
2189 SA_DBG1(("mpiInitialize:SPCV12G - offset MAIN_IO_ABORT_DELAY 0x%x value MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE 0x%x\n",MAIN_IO_ABORT_DELAY ,MAIN_IO_ABORT_DELAY_END_TO_END_CRC_DISABLE));
2190 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC OFF for rev A %d\n",smIsCfgVREV_A(agRoot) ));
2194 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC ON rev B %d ****************************\n",smIsCfgVREV_B(agRoot) ));
2201 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC on rev C %d\n",smIsCfgVREV_C(agRoot) ));
2207 SA_DBG1(("mpiInitialize:SPCV12G - END_TO_END_CRC Off unknown rev 0x%x\n", ossaHwRegReadConfig32((agRoot), 8 )));
2262 SA_DBG1(("mpiInitialize: A saveOffset 0x%x MSGUCfgTblDWIdx 0x%x\n",saveOffset ,MSGUCfgTblDWIdx));
2298 SA_DBG1(("mpiInitialize: ERROR The memory region does not have the right size for this inbound queue"));
2317 SA_DBG1(("mpiInitialize: queue %d PI CI zero\n",qIdx));
2406 SA_DBG1(("ERROR: The memory region does not have the right size for this outbound queue"));
2524 SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset )));
2528 SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE 0x%08X\n", 0));
2529 SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_GST_OFFSET) & 0xFFFF )));
2530 SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_IBQ_OFFSET) & 0xFFFF)));
2531 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_OBQ_OFFSET) & 0xFFFF)));
2532 SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_ANALOG_SETUP_OFFSET) & 0xFFFF )));
2533 SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_INT_VEC_TABLE_OFFSET) & 0xFFFF)));
2534 SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET) & 0xFFFF)));
2535 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 0x%08X\n", (ossaHwRegReadExt(agRoot, pcibar, TableOffset+MAIN_MOQFOT_MOQFOES) & 0xFFFF)));
2548 SA_DBG1(("mpiInitialize: mpiContextTable TableOffset 0x%08X contains 0x%08X\n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset )));
2553 SA_DBG1(("mpiInitialize: TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50));
2558 SA_DBG1(("mpiInitialize: MPITableType 0x%x context->offset 0x%x context->value 0x%x\n",context->MPITableType,context->offset,context->value));
2566 SA_DBG1(("mpiInitialize: AGSA_MPI_MAIN_CONFIGURATION_TABLE %d 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset, context->offset, context->value));
2571 SA_DBG1(("mpiInitialize: AGSA_MPI_GENERAL_STATUS_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType ,TableOffset+MAIN_GST_OFFSET, context->offset, context->value ));
2576 SA_DBG1(("mpiInitialize: AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_IBQ_OFFSET, context->offset, context->value));
2581 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_OBQ_OFFSET, context->offset, context->value));
2586 SA_DBG1(("mpiInitialize: AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_ANALOG_SETUP_OFFSET, context->offset, context->value));
2591 SA_DBG1(("mpiInitialize: AGSA_MPI_INTERRUPT_VECTOR_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_INT_VEC_TABLE_OFFSET, context->offset, context->value));
2596 SA_DBG1(("mpiInitialize: AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_PHY_ATTRIBUTE_OFFSET, context->offset, context->value));
2601 SA_DBG1(("mpiInitialize: AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE %d offset 0x%x + 0x%x = 0x%x\n",context->MPITableType,TableOffset+MAIN_MOQFOT_MOQFOES, context->offset, context->value));
2606 SA_DBG1(("mpiInitialize: error MPITableType unknown %d offset 0x%x value 0x%x\n",context->MPITableType, context->offset, context->value));
2613 SA_DBG1(("mpiInitialize: MAIN_AWT_MIDRANGE 0x%08X\n",
2632 SA_DBG1(("mpiInitialize: context %p saRoot->swConfig.mpiContextTable %p %d\n",context,saRoot->swConfig.mpiContextTable,context == saRoot->swConfig.mpiContextTable ? 1 : 0));
2636 SA_DBG1(("mpiInitialize:TableOffset 0x%x reads 0x%x expect 0x%x \n",TableOffset,ossaHwRegReadExt(agRoot, pcibar, TableOffset ),0x53434D50));
2652 SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE (0x%X) \n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET)));
2656 SA_DBG1(("mpiInitialize: SPC_MSGU_CFG_TABLE_UPDATE not set (0x%X)\n", siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET)));
2684 SA_DBG1(("mpiInitialize: mpiStartToggleFailed count %d\n", mpiStartToggleFailed));
2692 SA_DBG1(("mpiInitialize: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue));
2695 SA_DBG1(("mpiInitialize: MPI State = 0x%x\n", GSTLenMPIS));
2707 SA_DBG1(("mpiInitialize: MPI State = 0x%x mpiUnInitFailed count %d\n", GSTLenMPIS & GST_MPI_STATE_MASK,mpiUnInitFailed));
2716 SA_DBG1(("mpiInitialize: Error Not GST_MPI_STATE_INIT MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK));
2727 SA_DBG1(("mpiInitialize: MPI Error = 0x%x\n", GSTLenMPIS));
2752 SA_DBG1(("mpiInitialize: Error,IQ0 or OQ0 have to enable\n"));
2771 SA_DBG1(("mpiInitialize: SPC V writes IQ %2d offset 0x%x\n",i ,circularIQ->PIPCIOffset));
2803 SA_DBG1(("mpiInitialize: upperEventLogAddress 0x%x\n", value));
2806 SA_DBG1(("mpiInitialize: lowerEventLogAddress 0x%x\n", value));
2809 SA_DBG1(("mpiInitialize: eventLogSize 0x%x\n", value));
2812 SA_DBG1(("mpiInitialize: eventLogOption 0x%x\n", value));
2813 SA_DBG1(("mpiInitialize: EventLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperEventLogAddress,saRoot->mainConfigTable.lowerEventLogAddress,saRoot->mainConfigTable.eventLogSize/4 ));
2817 SA_DBG1(("mpiInitialize: upperIOPLogAddress 0x%x\n", value));
2820 SA_DBG1(("mpiInitialize: lowerIOPLogAddress 0x%x\n", value));
2821 SA_DBG1(("mpiInitialize: IOPLog dd /p %08X`%08X L %x\n",saRoot->mainConfigTable.upperIOPeventLogAddress,saRoot->mainConfigTable.lowerIOPeventLogAddress,saRoot->mainConfigTable.IOPeventLogSize/4 ));
2824 SA_DBG1(("mpiInitialize: IOPeventLogSize 0x%x\n", value));
2827 SA_DBG1(("mpiInitialize: IOPeventLogOption 0x%x\n", value));
2849 SA_DBG1(("mpiInitialize: hwConfig->hwOption %X\n", saRoot->hwConfig.hwOption ));
2851 SA_DBG1(("mpiInitialize: FatalErrorInterrupt 0x%x\n", value));
2856 SA_DBG1(("mpiInitialize: FatalErrorDumpOffset0 0x%x\n", value));
2859 SA_DBG1(("mpiInitialize: FatalErrorDumpLength0 0x%x\n", value));
2862 SA_DBG1(("mpiInitialize: FatalErrorDumpOffset1 0x%x\n", value));
2865 SA_DBG1(("mpiInitialize: FatalErrorDumpLength1 0x%x\n", value));
2870 SA_DBG1(("mpiInitialize: PortRecoveryTimerPortResetTimer 0x%x\n", value));
2874 SA_DBG1(("mpiInitialize: InterruptReassertionDelay 0x%x\n", value));
2883 SA_DBG1(("mpiInitialize: SCRATCH_PAD1_V_ERROR_STAT 0x%x\n",sp1 ));
2928 SA_DBG1(("mpiWaitForConfigTable: Waiting for SPC FW becoming ready.P1 0x%X P2 0x%X\n",value,value1));
2934 SA_DBG1(("mpiWaitForConfigTable: AAP error state and code 0x%x, ScratchPad2=0x%x\n", value, value1));
2936 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0)));
2937 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3)));
2947 SA_DBG1(("mpiWaitForConfigTable: IOP error state and code 0x%x, ScratchPad1=0x%x\n", value1, value));
2949 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0)));
2950 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3)));
2961 SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad1 0x%x\n", value));
2962 SA_DBG1(("mpiWaitForConfigTable: ScratchPad0 AAP error code 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0)));
2964 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD2 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_2,MSGU_SCRATCH_PAD_0)));
2965 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3)));
2975 SA_DBG1(("mpiWaitForConfigTable: wrong state failure, scratchPad2 0x%x\n", value1));
2976 SA_DBG1(("mpiWaitForConfigTable: ScratchPad3 IOP error code 0x%x\n",siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3) ));
2978 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0)));
2979 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD1 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_1,MSGU_SCRATCH_PAD_1)));
2998 SA_DBG1(("mpiWaitForConfigTable:VEN_DEV_SPCV force SCRATCH_PAD2 RDY 1 %08X 2 %08X\n" ,value,value1));
3004 SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1));
3011 SA_DBG1(("mpiWaitForConfigTable: timeout failure\n"));
3013 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0)));
3014 SA_DBG1(("mpiWaitForConfigTable: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3)));
3025 SA_DBG1(("mpiWaitForConfigTable: HDA mode set in SEEPROM SP1 0x%X\n",value));
3030 SA_DBG1(("mpiWaitForConfigTable: Waiting for _V_ FW becoming ready.P1 0x%X P2 0x%X\n",value,value1));
3044 SA_DBG1(("mpiWaitForConfigTable: Timeout!! SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1));
3053 SA_DBG1(("mpiWaitForConfigTable: FW Ready, SCRATCH_PAD1/2 value = 0x%x 0x%x\n", value, value1));
3068 SA_DBG1(("mpiWaitForConfigTable: smIS_spc8081 PCI BAR is not BAR4, bar=0x%x - failure\n", MSGUCfgTblBase));
3077 SA_DBG1(("mpiWaitForConfigTable: PCI BAR is not BAR5, bar=0x%x - failure\n", MSGUCfgTblBase));
3095 SA_DBG1(("mpiWaitForConfigTable: Signature value = 0x%x\n", Signature));
3148 SA_DBG1(("mpiWaitForConfigTable: INT Vector Tble Offset = 0x%x\n", config->InterruptVecTblOffset));
3149 SA_DBG1(("mpiWaitForConfigTable: Phy Attribute Tble Offset = 0x%x\n", config->phyAttributeTblOffset));
3162 SA_DBG1(("mpiWaitForConfigTable: Interface Revision value = 0x%08x\n", config->InterfaceRev));
3163 SA_DBG1(("mpiWaitForConfigTable: FW Revision value = 0x%08x\n", config->FWRevision));
3167 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n", STSDK_LL_SPC_VERSION));
3171 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_VERSION ));
3175 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%08x\n",STSDK_LL_12G_VERSION ));
3178 SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO value = 0x%08x\n", config->MaxOutstandingIO));
3179 SA_DBG1(("mpiWaitForConfigTable: MDevMaxSGL value = 0x%08x\n", config->MDevMaxSGL));
3180 SA_DBG1(("mpiWaitForConfigTable: ContrlCapFlag value = 0x%08x\n", config->ContrlCapFlag));
3181 SA_DBG1(("mpiWaitForConfigTable: GSTOffset value = 0x%08x\n", config->GSTOffset));
3182 SA_DBG1(("mpiWaitForConfigTable: inboundQueueOffset value = 0x%08x\n", config->inboundQueueOffset));
3183 SA_DBG1(("mpiWaitForConfigTable: outboundQueueOffset value = 0x%08x\n", config->outboundQueueOffset));
3184 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset0 value = 0x%08x\n", config->FatalErrorDumpOffset0));
3185 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength0 value = 0x%08x\n", config->FatalErrorDumpLength0));
3186 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpOffset1 value = 0x%08x\n", config->FatalErrorDumpOffset1));
3187 SA_DBG1(("mpiWaitForConfigTable: FatalErrorDumpLength1 value = 0x%08x\n", config->FatalErrorDumpLength1));
3190 SA_DBG1(("mpiWaitForConfigTable: HDAModeFlags value = 0x%08x\n", config->HDAModeFlags));
3191 SA_DBG1(("mpiWaitForConfigTable: analogSetupTblOffset value = 0x%08x\n", config->analogSetupTblOffset));
3199 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev));
3203 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev));
3214 SA_DBG1(("mpiWaitForConfigTable: 12g V sTSDK interface ver. 0x%x does not match InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev));
3218 SA_DBG1(("mpiWaitForConfigTable: V sTSDK interface ver. 0x%x incompatible with InterfaceRev 0x%x warning!\n", STSDK_LL_12G_INTERFACE_VERSION, config->InterfaceRev));
3230 SA_DBG1(("mpiWaitForConfigTable: SPC sTSDK interface ver. 0x%08x not compatible with InterfaceRev 0x%x warning!\n", STSDK_LL_INTERFACE_VERSION, config->InterfaceRev));
3242 SA_DBG1(("mpiWaitForConfigTable:6 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_VERSION, config->FWRevision));
3248 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision));
3254 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_VERSION, config->FWRevision));
3261 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_VERSION , config->FWRevision));
3267 SA_DBG1(("mpiWaitForConfigTable:12 sTSDK ver. sa.h 0x%08x config 0x%08x\n", STSDK_LL_12G_VERSION, config->FWRevision));
3273 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision));
3279 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_12G_VERSION, config->FWRevision));
3286 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_12G_VERSION , config->FWRevision));
3297 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x hadn't tested with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision));
3302 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x not compatible with FW ver. 0x%08x warning!\n", STSDK_LL_SPC_VERSION, config->FWRevision));
3309 SA_DBG1(("mpiWaitForConfigTable: sTSDK ver. 0x%x mismatch with FW ver. 0x%08x warning!\n",STSDK_LL_SPC_VERSION , config->FWRevision));
3314 SA_DBG1(("mpiWaitForConfigTable: ILA version 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_ILAT_ILAV_ILASMRN_ILAMRN_ILAMJN) ));
3321 SA_DBG1(("mpiWaitForConfigTable: MAIN_INACTIVE_ILA_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_INACTIVE_ILA_REVSION) ));
3322 SA_DBG1(("mpiWaitForConfigTable: MAIN_SEEPROM_REVSION 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_SEEPROM_REVSION) ));
3330 SA_DBG1(("mpiWaitForConfigTable: MAIN_AWT_MIDRANGE 0x%08X\n", ossaHwRegReadExt(agRoot, pcibar, (bit32)CfgTblDWIdx + MAIN_AWT_MIDRANGE) ));
3350 SA_DBG1(("mpiWaitForConfigTable: hwRevision 0x%x\n",saRoot->ControllerInfo.hwRevision ));
3365 SA_DBG1(("mpiWaitForConfigTable: MaxOutstandingIO 0x%x swConfig->maxActiveIOs 0x%x\n", config->MaxOutstandingIO,saRoot->swConfig.maxActiveIOs ));
3402 SA_DBG1(("mpiWaitForConfigTable: Signature = 0x%x\n", Signature));
3403 SA_DBG1(("mpiWaitForConfigTable: hwRevision = 0x%x\n", saRoot->ControllerInfo.hwRevision));
3404 SA_DBG1(("mpiWaitForConfigTable: FW Revision = 0x%x\n", config->FWRevision));
3405 SA_DBG1(("mpiWaitForConfigTable: Max Sgl = 0x%x\n", saRoot->ControllerInfo.maxSgElements));
3406 SA_DBG1(("mpiWaitForConfigTable: Max Device = 0x%x\n", saRoot->ControllerInfo.maxDevices));
3407 SA_DBG1(("mpiWaitForConfigTable: Queue Support = 0x%x\n", saRoot->ControllerInfo.queueSupport));
3408 SA_DBG1(("mpiWaitForConfigTable: Phy Count = 0x%x\n", saRoot->ControllerInfo.phyCount));
3409 SA_DBG1(("mpiWaitForConfigTable: sas Specs Support = 0x%x\n", saRoot->ControllerInfo.sasSpecsSupport));
3416 SA_DBG1(("mpiWaitForConfigTable: return 0x%x not AGSA_RC_SUCCESS warning!\n", ret));
3444 SA_DBG1(("mpiUnInitConfigTable: agRoot %p\n",agRoot));
3454 SA_DBG1(("mpiUnInitConfigTable: MSGUCfgTblBase = 0x%x AGSA_RC_FAILURE\n",MSGUCfgTblBase));
3481 SA_DBG1(("mpiUnInitConfigTable: TIMEOUT:IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue));
3502 SA_DBG1(("mpiUnInitConfigTable:AGSA_RC_FAILURE GSTOffset = 0x%x\n",GSTOffset));
3515 SA_DBG1(("mpiUnInitConfigTable: TIMEOUT, MPI State = 0x%x\n", GSTLenMPIS & GST_MPI_STATE_MASK));
3518 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD0 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_0)));
3519 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD1 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_1)));
3520 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD2 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_2)));
3521 SA_DBG1(("mpiUnInitConfigTable: SCRATCH_PAD3 value = 0x%x\n", ossaHwRegReadExt(agRoot, PCIBAR0, MSGU_SCRATCH_PAD_3)));
3716 SA_DBG1(("mpiReadGSTable: Chip PCI dead TableOffset 0x%x\n", TableOffset));
3720 // SA_DBG1(("mpiReadGSTable: TableOffset 0x%x\n", TableOffset));
3730 // SA_DBG1(("mpiReadGSTable: GSTableOffset 0x%x\n",GSTableOffset ));
4214 SA_DBG1(("mpiWrAnalogSetupTable:Analogtable Base Offset %08X pcibar %d\n",AnalogTableBase, pcibar ));
4216 SA_DBG1(("mpiWrAnalogSetupTable:%d %d\n",(int)sizeof(agsaPhyAnalogSetupRegisters_t), AnalogtableSize));
4269 SA_DBG1(("mpiWrIntVecTable: Base Offset %08X\n",(bit32)(INTVTableOffset + INT_VT_Coal_CNT_TO ) ));
4333 SA_DBG1(("mpiWrPhyAttrbTable: PHYTableOffset 0x%08x\n", PHYTableOffset));
4348 SA_DBG1(("mpiWrPhyAttrbTable: OQ Event per phy[%x] 0x%x\n", i, value));
4381 SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD0 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_0,MSGU_SCRATCH_PAD_0)));
4382 SA_DBG1(("mpiFreezeInboundQueue: SCRATCH_PAD3 value = 0x%x\n", siHalRegReadExt(agRoot, GEN_MSGU_SCRATCH_PAD_3,MSGU_SCRATCH_PAD_3)));
4414 SA_DBG1(("mpiFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue));
4477 SA_DBG1(("mpiUnFreezeInboundQueue: IBDB value/toggle = 0x%x 0x%x\n", value, togglevalue));
4493 SA_DBG1(("si_check_V_HDA: hda_status 0x%08X\n",hda_status ));
4498 SA_DBG1(("si_check_V_HDA: HDA mode, value = 0x%x\n", hda_status));
4522 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_ILA_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_ILA_MASK, SCRATCH_PAD1));
4536 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_RAAE_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_RAAE_MASK, SCRATCH_PAD1));
4551 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP0_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP0_MASK ,SCRATCH_PAD1));
4567 SA_DBG1(("si_check_V_Ready: SCRATCH_PAD1_V_IOP1_MASK (0x%x) not set SCRATCH_PAD1 = 0x%x\n",SCRATCH_PAD1_V_IOP1_MASK, SCRATCH_PAD1));
4588 SA_DBG1(("siScratchDump: SCRATCH_PAD 0 0x%08x 1 0x%08x 2 0x%08x 3 0x%08x\n",SCRATCH_PAD0,SCRATCH_PAD1,SCRATCH_PAD2,SCRATCH_PAD3 ));
4592 SA_DBG1(("siScratchDump: SCRATCH_PAD1 SCRATCH_PAD1_V_RESERVED 0x%08x\n", SCRATCH_PAD1_V_RESERVED));
4598 SA_DBG1(("siScratchDump: SCRATCH_PAD1 valid 0x%08x\n",SCRATCH_PAD0 ));
4599 SA_DBG1(("siScratchDump: RAAE ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_RAAE_MASK));
4603 SA_DBG1(("siScratchDump: ILA ready 0x%08x\n", SCRATCH_PAD1 & SCRATCH_PAD1_V_ILA_MASK));
4608 SA_DBG1(("siScratchDump: BOOTSTATE not success 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK));
4613 SA_DBG1(("siScratchDump: IOP0 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP0_MASK));
4617 SA_DBG1(("siScratchDump: IOP1 ready 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_IOP1_MASK ));
4621 SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_READY 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_READY ));
4625 SA_DBG1(("siScratchDump: SCRATCH_PAD1_V_BOOTSTATE_MASK 0x%08x\n",SCRATCH_PAD1 & SCRATCH_PAD1_V_BOOTSTATE_MASK ));
4636 SA_DBG1(("si_macro_check:smIS_SPC %d\n",smIS_SPC(agRoot) ));
4637 SA_DBG1(("si_macro_check:smIS_HIL %d\n",smIS_HIL(agRoot) ));
4638 SA_DBG1(("si_macro_check:smIS_SFC %d\n",smIS_SFC(agRoot) ));
4640 SA_DBG1(("si_macro_check:smIS_spc8001 %d\n",smIS_spc8001(agRoot) ));
4641 SA_DBG1(("si_macro_check:smIS_spc8081 %d\n",smIS_spc8081(agRoot) ));
4643 SA_DBG1(("si_macro_check:smIS_SPCV8008 %d\n",smIS_SPCV8008(agRoot) ));
4644 SA_DBG1(("si_macro_check:smIS_SPCV8009 %d\n",smIS_SPCV8009(agRoot) ));
4645 SA_DBG1(("si_macro_check:smIS_SPCV8018 %d\n",smIS_SPCV8018(agRoot) ));
4646 SA_DBG1(("si_macro_check:smIS_SPCV8019 %d\n",smIS_SPCV8019(agRoot) ));
4647 SA_DBG1(("si_macro_check:smIS_ADAP8088 %d\n",smIS_ADAP8088(agRoot) ));
4648 SA_DBG1(("si_macro_check:smIS_ADAP8089 %d\n",smIS_ADAP8089(agRoot) ));
4649 SA_DBG1(("si_macro_check:smIS_SPCV8070 %d\n",smIS_SPCV8070(agRoot) ));
4650 SA_DBG1(("si_macro_check:smIS_SPCV8071 %d\n",smIS_SPCV8071(agRoot) ));
4651 SA_DBG1(("si_macro_check:smIS_SPCV8072 %d\n",smIS_SPCV8072(agRoot) ));
4652 SA_DBG1(("si_macro_check:smIS_SPCV8073 %d\n",smIS_SPCV8073(agRoot) ));
4653 SA_DBG1(("si_macro_check:smIS_SPCV8074 %d\n",smIS_SPCV8074(agRoot) ));
4654 SA_DBG1(("si_macro_check:smIS_SPCV8075 %d\n",smIS_SPCV8075(agRoot) ));
4655 SA_DBG1(("si_macro_check:smIS_SPCV8076 %d\n",smIS_SPCV8076(agRoot) ));
4656 SA_DBG1(("si_macro_check:smIS_SPCV8077 %d\n",smIS_SPCV8077(agRoot) ));
4657 SA_DBG1(("si_macro_check:smIS_SPCV9015 %d\n",smIS_SPCV9015(agRoot) ));
4658 SA_DBG1(("si_macro_check:smIS_SPCV9060 %d\n",smIS_SPCV9060(agRoot) ));
4659 SA_DBG1(("si_macro_check:smIS_SPCV %d\n",smIS_SPCV(agRoot) ));
4661 SA_DBG1(("si_macro_check:smIS64bInt %d\n", smIS64bInt(agRoot) ));